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MAX9236 Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX9236 Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 15 page MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 7 Maxim Integrated Detailed Description The MAX9234/MAX9236 operate at a parallel clock fre- quency of 8MHz to 34MHz. The MAX9238 operates at a parallel clock frequency of 16MHz to 66MHz. The tran- sition times of the single-ended outputs are increased on the MAX9234/MAX9236 for reduced EMI. DC Balance Data coding by the MAX9209/MAX9211/MAX9213/ MAX9215 serializers (which are companion devices to the MAX9234/MAX9236/MAX9238 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the varia- tion in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. The maxi- mum DSV for the clock channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on AC-coupled links. To obtain DC balance on the data channels, the serial- izer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9234/ MAX9236/MAX9238 deserializers whether the data bits are inverted (see Figure 9). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC balance. AC-Coupling Benefits Bit errors experienced with DC-coupling can be elimi- nated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the com- mon-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS dri- ver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0 to 2.4V, allowing approximately ±1V common-mode differ- ence between the driver and receiver on a DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V). Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than ±1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage differ- ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-bal- anced coding of the data is required to maintain the dif- ferential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However, two capacitors—one at the serializer output and one at the deserializer input—provide protection in case either end of the cable is shorted to a high voltage. RIN1 RxIN_ + OR RxCLK IN+ RxIN_ - OR RxCLK IN- RIN1 1.2V Figure 1. LVDS Input Circuit RCIP RxCLK OUT ODD RxOUT EVEN RxOUT RISING-EDGE STROBE SHOWN. Figure 2. Worst-Case Test Pattern Table 1. Part Equivalent Table PART EQUIVALENT WITH DCB/NC = HIGH OR OPEN OPERATING FREQUENCY (MHz) OUTPUT STROBE MAX9234 MAX9210 8 to 34 Rising edge MAX9236 MAX9220 8 to 34 Falling edge MAX9238 MAX9222 16 to 66 Falling edge |
Similar Part No. - MAX9236_12 |
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Similar Description - MAX9236_12 |
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