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HT46RB50 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc |
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HT46RB50 Datasheet(HTML) 8 Page - Holtek Semiconductor Inc |
8 / 52 page HT46RB50 Rev. 1.40 8 February 23, 2012 At a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of the subroutine or an interrupt rou- tine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure more easily. If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 238 ´8 bits, and is divided into two functional groups, namely; spe- cial function registers (46 ´8 bits) and general purpose data memory (192 ´8 bits) most of which are read- able/writeable, although some are read only. The unused space before 40H is reserved for future ex- panded usage and reading these locations will get ²00H². The general purpose data memory, addressed from 40H to FFH, is used for data and control informa- tion under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- eration of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading lo- cation 00H or 02H indirectly returns the result 00H. While, writing into it, indirectly leads to no operation. The function of data movement between two indirect ad- dressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Accumulator - ACC The accumulator is closely related to ALU operations. It is also mapped to location 05H of the RAM and capable of operating with immediate data. The data movement between two data memory locations must pass through the accumulator. S p e c i a l P u r p o s e D a t a M e m o r y 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H : U n u s e d R e a d a s " 0 0 " G e n e r a l P u r p o s e D a t a M e m o r y ( 1 9 2 B y t e s ) 4 0 H 3 F H I n d i r e c t A d d r e s s i n g R e g i s t e r 0 M P 0 I n d i r e c t A d d r e s s i n g R e g i s t e r 1 M P 1 A C C P C L T B L P T B L H S T A T U S I N T C 0 T M R 0 T M R 0 C T M R 1 H T M R 1 L T M R 1 C P A P A C P B P B C P C P C C P D P D C P E P E C I N T C 1 U S C U S R U C C A W R S T A L L S I E S M I S C S E T I O F I F O 0 F I F O 1 F I F O 2 F I F O 3 A D R L A D R H A D C R A C S R P W M 0 P W M 1 S B C R S B D R 3 A H F F H RAM Mapping |
Similar Part No. - HT46RB50_12 |
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Similar Description - HT46RB50_12 |
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