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HT46RB50 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT46RB50 Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 52 page  HT46RB50 Rev. 1.40 10 February 23, 2012 The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of the INTC0), caused by a Timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of the INTC0), caused by a Timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC1) will be set. · The access of the corresponding USB FIFO from PC · The USB suspend signal from the PC · The USB resume signal from the PC · USB Reset signal When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca- tion 10H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When PC Host access the FIFO of the HT46RB50, the corresponding request bit of USR is set, and a USB inter- rupt is triggered. So user can easily determine which FIFO is accessed. When the interrupt has been served, the cor- responding bit should be cleared by firmware. When the HT46RB50 receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT46RB50 is set and a USB interrupt is also triggered. Also when the HT46RB50 receives a Resume signal from the Host PC, the resume line (bit3 of the ) of the HT46RB50 is set and a USB interrupt is triggered. Whenever a USB reset signal is detected, a USB inter- rupt is triggered. The A/D converter interrupt is controlled by setting the A/D interrupt control bit (EADI; bit 1 of the INTC1). When the interrupt is enabled, the stack is not full and the A/D conversion is finished, a subroutine call to location 14H will occur. The related interrupt request flag ADF (bit5 of the INTC1) will be reset and the EMI bit cleared to dis- able further interrupts. The serial interface interrupt is indicated by the interrupt flag (SIF; bit 6 of the INTC1), that is caused by a recep- tion or a complete transmission of an 8-bit data between the HT46RB50 and an external device. The serial inter- face interrupt is controlled by setting the Serial interface interrupt control bit (ESII ; bit 2 of the INTC1). After the interrupt is enabled (by setting SBEN; bit 4 of the SBCR), and the stack is not full and the SIF is set, a sub- routine call to location 18H occurs. Bit No. Label Function 0 EMI Controls the master (global) interrupt (1= enable; 0= disable) 1 EEI Controls the external interrupt (1= enable; 0= disable) 2 ET0I Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable) 3 ET1I Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable) 4 EIF External interrupt request flag (1= active; 0= inactive) 5 T0F Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) 6 T1F Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) 7 ¾ Unused bit, read as ²0² INTC0 (0BH) Register Bit No. Label Function 0 EUI Control the USB interrupt (1= enable; 0= disable) 1 EADI Control the A/D converter interrupt (1= enable; 0=disable) 2 ESII Control Serial interface interrupt (1= enable; 0= disable) 3, 7 ¾ Unused bit, read as ²0² 4 USBF USB interrupt request flag (1= active; 0= inactive) 5 ADF A/D converter request flag (1= active; 0= inactive) 6 SIF Serial interface interrupt request flag (1= active; 0= inactive) INTC1 (1EH) Register |
Similar Part No. - HT46RB50_12 |
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Similar Description - HT46RB50_12 |
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