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HT82M99E Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT82M99E Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 50 page  HT82M99E/HT82M99A Rev. 2.60 11 April 1, 2011 by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with tempera- tures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5V. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are re- served for user defined flags, which can only be set to ²10000² (WDTS.7~WDTS.3). If the device operates in a noisy environment, using the on-chip 32kHz RC oscillator (WDT OSC) is strongly rec- ommended, since the HALT will stop the system clock. WS2 WS1 WS0 Division Ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 WDTS (09H) Register The WDT overflow under normal operation will initialize a ²chip reset² and set the status bit ²TO². But in the HALT mode, the overflow will initialize a ²warm reset² and only the program counter and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a ²HALT² in- struction. The software instruction include ²CLR WDT² and the other set -²CLR WDT1² and ²CLR WDT2².Of these two types of instruction, only one can be active de- pending on the ROM code option -²CLR WDT times se- lection option ².Ifthe ²CLR WDT² is selected (i.e. CLRWDT times is equal to one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR WDT² and ²CLR WDT² are chosen (i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the ²HALT² instruction and results in the following: · The system oscillator will be turned off but the WDT oscillator remains running (if the WDT oscillator is se- lected). · The contents of the on-chip RAM and registers remain unchanged. · The WDT and WDT prescaler will be cleared and re- counted again (if the WDT clock is from the WDT os- cillator). · All of the I/O ports remain in their original status. · The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow per- forms a ²warm reset². After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or exe- cuting the ²CLR WDT² instruction and is set when exe- cuting the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be con- sidered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stim- ulus, the program will resume execution of the next in- struction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the inter- rupt is enabled but the stack is full, the program will re- sume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt re- sponse takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up func- tion of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, S y s t e m C l o c k / 4 8 - b i t C o u n t e r W D T P r e s c a l e r 7 - b i t C o u n t e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 R O M C o d e O p t i o n S e l e c t W D T O S C Watchdog Timer |
Similar Part No. - HT82M99E_11 |
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Similar Description - HT82M99E_11 |
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