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UM10601 Datasheet(PDF) 9 Page - NXP Semiconductors |
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UM10601 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 313 page UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary user manual Rev. 1.0 — 7 November 2012 9 of 313 NXP Semiconductors UM10601 Chapter 2: LPC800 Memory mapping 2.2.1 Memory mapping 2.2.2 Micro Trace Buffer (MTB) The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer. The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. LPC800 Memory mapping $3%SHULSKHUDOV [ [ [& [ [ [ [ [ [& [ [ [ [& [ [ [& [ [ [ [ [& [ [ ::'7 057 VHOIZDNHXSWLPHU 308 UHVHUYHG DQDORJFRPSDUDWRU [& UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG [ [ UHVHUYHG UHVHUYHG [ *% *% *% *% [ [))) [))) [ [ [ [)))))))) UHVHUYHG UHVHUYHG UHVHUYHG [ [ $3%SHULSKHUDOV [ [$ [$ &5& 6&7 *3,2 [$ SLQLQWHUUXSWVSDWWHUQPDWFK [ N%65$0/3& [ N%65$0/3& [ N%65$0/3& [ [ N%07% /3& [ [ [ N%RQFKLSIODVK/3& N%RQFKLSIODVK/3& N%RQFKLSIODVK/3& N%ERRW520 [ [& DFWLYHLQWHUUXSWYHFWRUV DDD UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG IODVKFRQWUROOHU 63, VZLWFKPDWUL[ ,2&21 6<6&21 [ 63, 86$57 [ 86$57 [& 86$57 [ [( [( SULYDWHSHULSKHUDOEXV ,& UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG |
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