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ICX059CL Datasheet(PDF) 3 Page - Sony Corporation |
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ICX059CL Datasheet(HTML) 3 Page - Sony Corporation |
3 / 18 page – 3 – ICX059CL Bias Conditions Item Output amplifier drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate clock voltage adjustment Protective transistor bias VDD VGG VSS VSUB ∆VSUB VRGL ∆VRGL VL 14.55 3.8 9.0 –3 1.0 –3 15.0 4.2 15.45 4.65 18.5 +3 4.0 +3 V V V % V % ±5% ∗1 ∗1, ∗6 Symbol Min. Typ. Max. Unit Remarks DC Characteristics Item Output amplifier drain current Input current Input current IDD IIN1 IIN2 5 1 10 mA µA µA ∗3 ∗4 Symbol Min. Typ. Max. Unit Remarks Grounded with 820 Ω resistor ∗2 ∗1 Indications of substrate voltage (V SUB ) · reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is ±3%. VSUB code one character indication VRGL code one character indication ↑ ↑ VRGL code VSUB code Code and optimal setting correspond to each other as follows. 1 VRGL code Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2 3 4 5 6 7 VSUB code Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 E f G h J K L m N P Q R S T U V W X Y Z <Example> “5L” → VRGL = 3.0V VSUB = 12.0V ∗2 V L setting is the VVL voltage of the vertical transfer clock waveform. ∗3 1) Current to each pin when 18V is applied to V DD , VOUT, Vss and SUB pins, while pins that are not tested are grounded. 2) Current to each pin when 20V is applied sequentially to V φ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin. 3) Current to each pin when 15V is applied sequentially to RG, LH φ1, Hφ1, Hφ2 and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin. 4) Current to VL pin when 30V is applied to V φ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied to RG pin or when, 20V is applied to VGG, Vss, H φ1, Hφ2 and LHφ1 pins, while VL pin is grounded. However, GND and SUB pins are left open. ∗4 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. |
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