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FOD8316V Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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FOD8316V Datasheet(HTML) 8 Page - Fairchild Semiconductor |
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8 / 29 page  ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.0 8 Notes: 16. This load condition approximates the gate load of a 1200 V/150A IGBT. 17. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse(VIN+, VIN-) to the 50% level of the falling edge of the VO signal. Refer to Figure 48. 18. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse (VIN+, VIN-) to the 50% level of the rising edge of the VO signal. Refer to Figure 48. 19. PWD is defined as | tPHL – tPLH | for any given device. 20. The difference between tPHL and tPLH between any two FOD8316 parts under same operating conditions, with equal loads. 21. This is the amount of time the DESAT threshold must be exceeded before VO begins to go low. This is supply voltage dependent. See Figure 49. 22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. See Figure 49. 23. This is the amount of time the DESAT threshold must be exceeded before VO begins to go low, and the FAULT output to go low. See Figure 49. 24. This is the amount of time from when RESET is asserted low, until FAULT output goes high. See Figure 49. 25. tUVLO ON UVLO Turn On Delay is measured from VUVLO+ threshold voltage of the output supply voltage (VDD2) to the 5V level of the rising edge of the VO signal. 26. tUVLO OFF UVLO Turn Off Delay is measured from VUVLO– threshold voltage of the output supply voltage (VDD2) to the 5V level of the falling edge of the VO signal. 27. tGP Time to Good Power is measured from 13.5V level of the rising edge of the output supply voltage (VDD2) to the 5V level of the rising edge of the VO signal. 28. Common mode transient immunity at output high state is the maximum tolerable negative dVCM/dt on the trailing edge of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). 29.Common mode transient immunity at output low state is the maximum positive tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V). tGP Time to Good Power(27) VDD2 = 0 to 30V in 10µs Ramp 30 µs 30, 31, 43 | CMH | Common Mode Transient Immunity at Output High TA = 25ºC, VDD1 = 5V, VDD2 = 25V, VSS = Ground, VCM = 1500Vpk (28) 35 50 kV/µs 45, 46 | CML | Common Mode Transient Immunity at Output Low TA = 25ºC, VDD1 = 5V, VDD2 = 25V, VSS = Ground, VCM = 1500Vpk (29) 35 50 kV/µs 44, 47 Symbol Parameter Conditions Min. Typ. Max. Units Figure Switching Characteristics (Continued) Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30V, VE – VSS = 0V, TA = 25°C unless otherwise specified. |
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