© 2011 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSA8108 • Rev. 1.0.0

20

Physical Dimensions

Figure 14.

12-Ball, 3x4 Array, 0.4mm Pitch, 250µm Ball, Wafer-Level Chip-Scale Package (WLCSP)

Nominal Values

Bump Pitch Overall Package Height

Silicon Thickness Solder Bump Height

Solder Bump Diameter

0.4mm

0.586mm

0.378mm

0.208mm

0.260mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which

covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

Ordering Information

Part Number

Operating

Temperature

Range

Top

Mark

Package

D

E

X

Y

FSA8108BUCX

-40 to +85°C

G6

12-Ball, 3x4 Array, 0.4mm Pitch, 250µm

Ball, Wafer-Level Chip-Scale Package

1.56mm 1.16mm 0.18mm 0.18mm

BOTTOM VIEW

SIDE VIEWS

TOP VIEW

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

G. DRAWING FILENAME: MKT-UC012ACrev1.

0.40

0.40

0.80

1.20

Ø0.260±0.02

12X

(X)±0.018

(Y)±0.018

A

B

C

D

12 3

2X

PIN 1 AREA

0.03 C

E

D

A

B

2X

0.03 C

0.05 C

0.625

0.547

C

0.378±0.018

0.208±0.021

SEATING PLANE

D

F

F

(Ø0.200)

Cu Pad

(Ø0.300)

Solder Mask

0.40

0.80

1.20

0.40

0.005

CA B