WM8259

Production Data

w

PD Rev 4.2 April 2007

6

ELECTRICAL CHARACTERISTICS

Test Conditions

°C, MCLK = 18MHz, mode 1 unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)

Full-scale input voltage range

(see Note 1)

Max Gain

Min Gain

0.25

2.56

Vp-p

Vp-p

Input signal limits (see Note 2)

0

AVDD

V

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

10

+50

mV

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

10

+50

mV

Differential non-linearity

DNL

1.25

LSB

Integral non-linearity

INL

24

LSB

Input referred noise

13

LSB rms

References

Upper reference voltage

VRT

2.05

V

Lower reference voltage

VRB

1.05

V

Diff. reference voltage (VRT-VRB)

0.95

1.0

1.05

V

Output resistance VRT, VRB, VRX

1

Ω

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

20

60

100

Ω

VRLC short-circuit current

1.6

2

4.5

mA

VRLC output resistance

2

Ω

VRLC Hi-Z leakage current

VRLC = 0 to AVDD

1

µA

RLCDAC resolution

4

bits

RLCDACRNG = 0

0.18

V/step

RLCDAC step size

RLCDACRNG = 1

0.123

V/step

RLCDACRNG = 0

0.3

V

RLCDAC output voltage at

code 0(hex)

RLCDACRNG = 1

0.2

V

RLCDACRNG = 0

3.0

V

RLCDAC output voltage at

code F(hex)

RLCDACRNG = 1

2.05

V

Offset DAC, Monotonicity Guaranteed

Resolution

8

bits

Differential non-linearity

DNL

0.2

LSB

Integral non-linearity

INL

0.6

LSB

Step size

2.03

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-260

+260

mV

mV

Notes:

1.

Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input

range.

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.