© 2011 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FT10001 • Rev 1.0.1

2

Block Diagram

Figure 1.

Block Diagram

Pin Configuration

Figure 2.

Pad Assignments (Top-Through View)

Pin Definitions

Pin #

Name

Description

Normal Operation

Zero-Second Factory-Test Mode

1

/RST1

Open-drain output, active LOW

Open-drain output, active LOW

2

GND

GND

GND

3

/SR0

Reset input with integrated pull-up, active LOW Reset input with integrated pull-up, active LOW

4

VCC

Power supply

Power supply

5

DSR

Delay selection input; tie to GND during normal

operation

.(1)

Delay selection input. Pull HIGH to enable Zero-

second delay for factory test.

6

TEST

Used for device testing; tie to GND during

normal operation.

Used for device testing; tie to GND during normal

operation.

Note:

1.

This pin must always be tied to either GND or VCC. It must not float.