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PPXS2010VLQ120R Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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PPXS2010VLQ120R Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 30 page Features PXS20 Product Brief, Rev. 1 Freescale Semiconductor 3 2.1 PXS20 Features Table 1 displays the PXS20 feature set. Table 1. PXS20 Family Feature Set Feature PXS20 CPU Type 2 × e200z4 (in lock-step or decoupled operation) Architecture Harvard Execution speed 0 – 120 MHz (+2% FM) DMIPS intrinsic performance > 240 MIPS SIMD (DSP + FPU) Yes MMU 16 entry Instruction set PPC Yes Instruction set VLE Yes Instruction cache 4 KB, EDC MPU-16 regions Yes, replicated module Semaphore unit (SEMA4) Yes Buses Core bus AHB, 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data Crossbar Master × slave ports Lock Step Mode: 4 × 3 Decoupled Parallel Mode: 6 × 3 Memory Code/data flash 1 MB, ECC, RWW Static RAM (SRAM) 128 KB, ECC Modules Interrupt controller (INTC) 16 interrupt levels, replicated module Periodic Interrupt Timer (PIT) 1 × 4 channels System timer module (STM) 1 × 4 channels, replicated module Software watchdog timer (SWT) Yes, replicated module eDMA 16 channels, replicated module FlexRay 1 × 64 message buffers, dual channel CAN 2 × 32 message buffers UART with DMA support 2 Clock out Yes Fault control & collection unit (FCCU) Yes Cross triggering unit (CTU) Yes eTimer 3 × 6 channels PWM 2 Module 4 × (2 + 1) channels Analog-to-digital converter (ADC) 2 × 12-bit ADC, 16 channels per ADC (3 internal, 4 shared and 9 external) |
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