PXS20 Product Brief, Rev. 1

Features

Freescale Semiconductor

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Reservation instruction to support read-modify-write constructs

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Extensive system development and tracing support via Nexus debug port

2.5.2

Crossbar Switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and

three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows four concurrent transactions to occur from any master port to any slave port, although

one of those transfers must be an instruction fetch from internal flash memory. If a slave port is

simultaneously requested by more than one master port, arbitration logic selects the higher priority master

and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the

higher priority master completes its transactions.

The crossbar provides the following features:

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4 masters and 3 slaves supported per each replicated crossbar

— Masters allocation for each crossbar: e200z4d core with two independent bus interface units

(BIU) for I and D access (2 masters), one eDMA, one FlexRay

— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to

guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM

controller with 1 slave port each and 1 redundant peripheral bus bridge

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32-bit address bus and 64-bit data bus

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Programmable arbitration priority

— Requesting masters can be treated with equal priority and are granted access to a slave port in

round-robin method, based upon the ID of the last master to be granted access or a priority

order can be assigned by software at application run time

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Temporary dynamic priority elevation of masters

The XBAR is replicated for each processor.

2.5.3

Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA,

FlexRay, CPU) can be assigned different access rights to each region.

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16-region MPU with concurrent checks against each master access

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32-byte granularity for protected address region

The memory protection unit is replicated for each processor.

2.5.4

Enhanced Direct Memory Access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of

performing complex data movements via 16 programmable channels, with minimal intervention from the

host processor. The hardware microarchitecture includes a DMA engine which performs source and

destination address calculations, and the actual data movement operations, along with an SRAM-based