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SPXD1010VLQ120R Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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SPXD1010VLQ120R Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 130 page  Overview PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 5 1.5 PXD10 features 1.5.1 Summary • Single issue, 32-bit Power Architecture technology compliant CPU core complex (e200z0h) — Compatible with Power Architecture instruction set — Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E compliant code • On-chip ECC flash memory with flash controller — As much as 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port — 64 KB data flash—separate 4 16 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port • As much as 48 KB on-chip ECC SRAM with SRAM controller • As much as 160 KB on-chip non-ECC graphics SRAM with SRAM controller • Memory Protection Unit (MPU) with as many as 12 region descriptors and 32-byte region granularity to provide basic memory access permission • Interrupt Controller (INTC) with as many as 127 peripheral interrupt sources and eight software interrupts • Two Frequency-Modulated Phase-Locked Loops (FMPLLs) — Primary FMPLL provides a 64 MHz system clock — Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation • Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters (AMBA 2.0 v6 AHB) • 16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA channel multiplexer • Boot Assist Module (BAM) supports internal flash programming via a serial link (FlexCAN or LINFlex) • Display Control Unit to drive TFT LCD displays — Includes processing of as many as four planes that can be blended together — Offers a direct unbuffered hardware bit-blitter of as many as 16 software-configurable dynamic layers in order to drastically minimize graphic memory requirements and provide fast animations — Programmable display resolutions are available up to WVGA • Parallel Data Interface (PDI) for digital video input • LCD segment driver module with two software programmable configurations: — As many as 40 frontplane drivers and four backplane drivers |
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