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MPXR3015VMS1R Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc

Part # MPXR3015VMS1R
Description  PXS30 Microcontroller
Download  139 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPXR3015VMS1R Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc

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Introduction
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
11
DDR 1
DDR 2 (optional)
•SDR
The controller has the following features:
Optimized timing for 32-byte bursts and single read accesses on the AHB interface
Optimized timing for 8-byte and 16-byte bursts on the DRAMC interface
Supports priority elevation on the slave ports for single accesses
16-bit wide DRAM interface
One chip select (CS)
mDDR memory controller
— 16-bit external interface
— Address range up to 8 MB
1.5.12
Boot Assist Module (BAM)
Enables booting via serial mode (FlexCAN, LINFlex)
Handles static mode in case of an erroneous boot procedure
Implemented in 8 KB ROM
Supports Lock Step Mode (LSM) and Decoupled Parallel Mode (DPM)
1.5.13
Parallel Data Interface (PDI)
Support for external ADC and CMOS image sensors
Parallel interface operation up to MCU system bus frequency
Selectable data capture from rising or falling edge
Receive FIFO with adjustable trigger thresholds
Data width for 8, 10, 12, 14, and 16 bits
Data Packing Unit to pack input data on 64-bit words — data packed on 8- or 16- bit boundary,
depending on input data width
Binary increasing channel select that allows as many as eight channels to be selected
Frame synchronization through Vsync, Hsync, PIXCLK
1.5.14
Deserial Serial Peripheral Interface (DSPI) modules
Three Serial Peripheral Interfaces
— Full duplex communication ports with interrupt and eDMA request support
— Support for all functional modes from QSPI submodule of QSMCM (MPC5xx family)
— Support for queues in RAM
— Six chip selects, expandable to 64 with external demultiplexers
— Programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis


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