© 2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN2110 • Rev. 1.0.4

3

Pin Configuration

Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)

Pin Definitions

Pin #

Name

Description

P1, 6-12

SW

Switching Node. Junction of high-side and low-side MOSFETs.

P2, 2-5

VIN

Power Conversion Input Voltage. Connect to the main input power source.

P3, 21-23

PGND

Power Ground. Power return and Q2 source.

1

BOOT

SW is LOW.

13

PGOOD

Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits

specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled.

14

EN

ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the

regulator after a latched fault condition. This input has an internal pull-up when the IC is

functioning normally. When a latched fault occurs, EN is discharged by a current sink.

15

VCC

Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin. This

pin should be decoupled to AGND through a > 2.2 µF X5R / X7R capacitor.

16

AGND

Analog Ground. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

17

ILIM

limit trip threshold lower than the internal default setting.

18

R(T)

frequency.

19

FB

Output Voltage Feedback. Connect through a resistor divider to the output voltage.

20

COMP

Compensation. Error amplifier output. Connect the external compensation network between

this pin and FB.

24

NC

No Connect. This pin is not used.

25

RAMP

and provides voltage feedforward functionality.