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ICX285AL Datasheet(PDF) 3 Page - Sony Corporation |
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ICX285AL Datasheet(HTML) 3 Page - Sony Corporation |
3 / 21 page – 3 – ICX285AL Ratings –40 to +12 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +22 –10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15 to +15 –6.5 to +6.5 –10 to +16 –30 to +80 –10 to +60 –10 to +75 Item VDD, VOUT, φRG – φSUB V φ2A, Vφ2B – φSUB Against φSUB V φ1, Vφ3, Vφ4, VL – φSUB H φ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Against GND V φ1, Vφ2A, Vφ2B, Vφ3, Vφ4 – GND H φ1, Hφ2 – GND Against VL V φ2A, Vφ2B – VL V φ1, Vφ3, Vφ4, Hφ1, Hφ2, GND – VL Between input Voltage difference between vertical clock input pins clock pins H φ1 – Hφ2 H φ1, Hφ2 – Vφ4 Storage temperature Performance guarantee temperature Operating temperature Absolute Maximum Ratings Unit V V V V V V V V V V V V V °C °C °C Remarks *1 *1 +24 V (Max.) when clock width < 10 µs, clock duty factor < 0.1%. +16 V (Max.) is guaranteed for power-on and power-off. Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 *2 *3 *3 Max. 15.45 Unit V Remarks DC characteristics Item Supply current Symbol IDD Min. Typ. 9 Max. 11 Unit mA Remarks *2 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. *3 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. |
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