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RT8206M Datasheet(PDF) 6 Page - Richtek Technology Corporation |
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RT8206M Datasheet(HTML) 6 Page - Richtek Technology Corporation |
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6 / 27 page  RT8206L/M 6 DS8206L/M-07 June 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Functional Pin Description REF (Pin 1) 2V Reference Output. Bypass to GND with a 0.22 μF capacitor. REF can source up to 50 μA for external loads. Loading REF degrades FBx and output accuracy according to the REF load-regulation error. TON (Pin 2) Frequency Select Input. (VOUT1/VOUT2 switching frequency, respectively) : TON = VCC, (200kHz / 300kHz) TON = REF, (300kHz / 400kHz) TON = GND, (400kHz / 500kHz) VCC (Pin 3) Analog Supply Voltage Input for the PWM Core. Bypass to GND with a 1 μF ceramic capacitor ENLDO (Pin 4) LDO Enable Input. REF and LDO are enabled if ENLDO is within logic high level and disabled if ENLDO is less than the logic low level. NC (Pin 5, 8) No Internal Connection. VIN (Pin 6) Power Supply Input. VIN is used for the constant on-time PWM one shot circuits. VIN is also used to power the linear regulators. The linear regulators are powered by SMPS1 if VOUT1 is set greater than 4.66V and BYP is tied to VOUT1. Connect VIN to the battery input and bypass with a 1 μF capacitor. LDO (Pin 7) Linear-Regulator Output. LDO can provide a total of 70mA external loads. The LDO regulates a fixed 5V output. When the BYP is within 5V switchover threshold, the internal regulator shuts down and the LDO output pin connects to BYP through a 1.5 Ω switch. Bypass LDO output with a minimum of 4.7 μF ceramic. BYP (Pin 9) Switchover Source Voltage Input for LDO. VOUT1 (Pin 10) SMPS1 Output Voltage Sense Input. Connect this pin to the SMPS1 output. VOUT1 is an input to the constant on-time-PWM one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode. FB1 (Pin 11) SMPS1 Feedback Input. Connect FB1 to VCC or GND for fixed 5V operation. Connect FB1 to a resistive voltage- divider from VOUT1 to GND to adjust output from 2V to 5.5V. ILIM1 (Pin 12) SMPS1 Current Limit Adjustment. The GND − PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a 0.5V to 2.5V range. There is an internal 5 μAcurrent source from VCC to ILIM1. The logic current limit threshold defaults to 100mV if ILIM1 is higher than (VCC − 1V). PGOOD1 (Pin 13) SMPS1 Power Good Open-Drain Output. PGOOD1 is low when the SMPS1 output voltage is more than 10% below the normal regulation point or during soft-start. PGOOD1 is in high impedance when the output is in regulation and the soft-start circuit has terminated. PGOOD1 is low in shutdown. EN1 (Pin 14) SMPS1 Enable Input. The SMPS1 will be enabled if EN1 is greater than the logic high level and disabled if EN1 is less than the logic low level. If EN1 is connected to REF, SMPS1 starts after SMPS2 reaches regulation (delay start). Drive EN1 below 0.8V to clear fault level and reset the fault latches. UGATE1 (Pin 15) High Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1. |
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