W25P243A-4A datasheet(3/18 Pages) WINBOND

Part #	W25P243A-4A

Description	64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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W25P243A

Publication Release Date: August 1999

- 3 -

Revision A3

PIN DESCRIPTION

SYMBOL

TYPE

DESCRIPTION

A0

−A15

Input, Synchronous

Host address

I/O1

−I/O64

I/O, Synchronous

Data Inputs/Outputs

CLK

Input, Clock

Processor host bus clock

CE1, CE2, CE3

Input, Synchronous

Chip enables

GW

Input, Synchronous

Global write

BWE

Input, Synchronous

Byte write enable from cache controller

BW1

−BW8

Input, Synchronous

Host bus byte enables used with BWE

OE

Input, Asynchronous

Output enable input

ADV

Input, Synchronous

Internal burst address counter advance

ADSC

Input, Synchronous

Address status from Chip Set

ADSP

Input, Synchronous

Address status from CPU

ZZ

Input, Asynchronous

Snooze pin for low-power state, internal pull low

LBO

Input, Static

Lower address burst order

Connected to VSS: Device is in linear mode.

Connected to VDD or unconnected: Device is in non-

linear mode.

VDDQ

I/O power supply

VSSQ

I/O ground

VDD

Power supply

VSS

Ground

RSV

Reserved pin, don't use these pins

NC

No connection

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