Preliminary W78C51D

Publication Release Date: January 1999

- 7 -

Revision A1

INT3 ).

Example: P4

REG

0D8H

MOV

P4, #0AH

; Output data "A" through P4.0

−P4.3.

MOV

A, P4

; Read P4 status to Accumulator.

SETB

P4.0

; Set bit P4.0

CLR

P4.1

; Clear bit P4.1

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide

the system clock. The divider output is selectable and determines the time-out interval. When the

time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog

timer is as a system monitor. This is important in real-time control applications. In case of power

glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is

left unchecked the entire system may crash. The watchdog time-out selection will result in different

time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In

general, software should restart the Watchdog timer to put it into a known state. The control bits that

support the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

3

2

1

0

ENW

CLRW

WIDL

-

-

PS2

PS1

PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.

CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0

0

0

2

0

1

0

4

0

0

1

8

0

1

1

16

1

0

0

32

1

0

1

64

1

1

0

128

1

1

1

256