Electronic Components Datasheet Search |
|
W78IE54P Datasheet(PDF) 6 Page - Winbond |
|
W78IE54P Datasheet(HTML) 6 Page - Winbond |
6 / 21 page Preliminary W78IE54 - 6 - 2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 , INT3 ). Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0 −P4.3. MOV A, P4 ; Read P4 status to Accumulator. SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1 3. Reduce EMI Emission Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78IE54 allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24MHz. The value of R and C1,C2 may need some adjustment while running at lower gain. ***AUXR - Auxiliary register (8EH) - - - - - - - AO AO: Turn off ALE output. 4. Power-off Flag ***PCON - Power control (87H) - - - POF GF1 GF0 PD IDL POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: Power down mode bit. Set it to enter power down mode. IDL: Idle mode bit. Set it to enter idle mode. The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. |
Similar Part No. - W78IE54P |
|
Similar Description - W78IE54P |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |