W78E54

Publication Release Date: November 1997

- 9 -

Revision A2

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E54 is used

with an external RC network. The reset logic also has a special glitch removal circuit that ignores

glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of

bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Option Setting

Users write programs into the W78E54 by using the Winbond proprietary writer. The writer programs

the data into an internal 16 KB region and reads the data back for verification. After confirming that

the program is correct, the user can lock the data so that they can no longer be read.

Lock Bit

This bit is used to protect the customer data in the W78E54. It may be turned on after the

programmer finishes the programming and verify sequence. Once this bit is set to logic 0, no flash

data can be accessed again.

MOVC Execute

This bit is used to restrict the region accessible to the MOVC instruction. It can prevent the program

from being downloaded using this instruction if the program needs to jump outside to get data. When

this bit is set to logic 0, a MOVC instruction in external program memory space

will

be

able

to

access code in the external memory, but it will not be able to access code in the internal memory. A

MOVC instruction in internal program memory space will always be able to access code in both

internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

1. INT2/ INT3

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register

is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2