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W83194R-67A Datasheet(PDF) 3 Page - Winbond |
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W83194R-67A Datasheet(HTML) 3 Page - Winbond |
3 / 18 page W83194R-67A PRELIMINARY Publication Release Date: Feb. 1999 - 3 - Revision 0.30 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k Ω pull-up 5.1 Crystal I/O SYMBOL PIN I/O FUNCTION Xin 4 IN Crystal input with internal loading capacitors and feedback resistors. Xout 5 OUT Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL PIN I/O FUNCTION CPUCLK_F 46 OUT Free running CPU clock. Not affected by CPU_STOP# CPUCLK[0:2] 45,43,42 OUT Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if CPU_STOP# is low. *CPU_STOP# 41 IN This asynchronous input halts CPUCLK[0:2] and SDRAM(0:11) at logic level when driven low. SDRAM_F 39 OUT Free running SDRAM clock. Not affected by CPU_STOP# SDRAM [ 0:11] 17,18,20,21,28 ,29,31,32,34, 35,37,38 OUT SDRAM clock outputs. Fanout buffer outputs from BUFFER IN pin.(Controlled by chipset) PCICLK_F/ *MODE 7 I/O Free running PCI clock during normal operation. Latched Input. Mode=1, Pin 2 is REF0; Mode=0, Pin2 is PCI_STOP# PCICLK0/*FS3 8 I/O Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCICLK [ 1:4 ] 10,11,12,13 OUT Low skew (< 250ps) PCI clock outputs. Synchronous to CPU clocks with 1/-4ns skew(CPU early). BUFFER IN 15 IN Inputs to fanout for SDRAM outputs. |
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