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W83194R-67B Datasheet(PDF) 8 Page - Winbond |
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W83194R-67B Datasheet(HTML) 8 Page - Winbond |
8 / 18 page W83194R-67B PRELIMINARY Publication Release Date: Dec.. 1999 - 8 - Revision 0.50 Frequency table by I2C SSEL3 SSEL2 SSEL1 SSEL 0 CPU,SDRA M(MHz) PCI(MHz) REF,IOAPIC (MHz) 1 1 1 1 60 30(CPU/2) 14.318 1 1 1 0 66.8 33.4(CPU/2) 14.318 1 1 0 1 70 35(CPU/2) 14.318 1 1 0 0 90 30(CPU/3) 14.318 1 0 1 1 97.0 32.33(CPU/3) 14.318 1 0 1 1 80 26.67(CPU/3) 14.318 1 0 1 0 83.3 27.77(CPU/3) 14.318 1 0 0 1 95.25 31.75(CPU/3) 14.318 1 0 0 0 100.2 33.3(CPU/3) 14.318 0 1 1 1 75 37.5(CPU/2) 14.318 0 1 1 0 80 40(CPU/2) 14.318 0 1 0 1 83.3 41.65(CPU/2) 14.318 0 1 0 0 105 35(CPU/3) 14.318 0 0 1 1 110 36.67(CPU/3) 14.318 0 0 1 0 115 38.33(CPU/3) 14.318 0 0 0 1 124 31(CPU/4) 14.318 0 0 0 0 133 33.3(CPU/4) 14.318 8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 x - Latched FS2# 6 1 - 0 = 0.5% down type spread, overrides Byte0 -bit7. 1= Center type spread. 5 1 - Reserved 4 1 - Reserved 3 1 42 CPUCLK2 (Active / Inactive) 2 1 43 CPUCLK1 (Active / Inactive) 1 1 45 CPUCLK0 (Active / Inactive) 0 1 46 CPUCLK_F (Active / Inactive) |
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