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W83877 Datasheet(PDF) 5 Page - Winbond |
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W83877 Datasheet(HTML) 5 Page - Winbond |
5 / 125 page W83877F Publication Release Date: January 1996 - 5 - Revision A2 1.0 PIN DESCRIPTION Note: Refer to section 9.2 DC CHARACTERISTICS for details. I/O8t - TTL level bidirectional pin with 8 mA source-sink capability I/O12t - TTL level bidirectional pin with 12 mA source-sink capability I/O24t - TTL level bidirectional pin with 24 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability OUT12t - TTL level output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INt - TTL level input pin INc - CMOS level input pin INcs - CMOS level schmitt-triggered input pin 1.1 Host Interface SYMBOL PIN I/O FUNCTION D0 −D7 66-73 I/O24t System data bus bits 0-7 A0 −A9 51-55 57-61 INc System address bus bits 0-9 A10 75 INc In ECP Mode, this pin is the A10 address input. IOCHRDY 5 OD24 In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. MR 6 INcs Master Reset. Active high. MR is low during normal operations. CS 2 INt Active low chip select signal AEN 62 INc System address bus enable IOR 63 INcs CPU I/O read signal IOW 64 INcs CPU I/O write signal DRQ_B 100 OUT12t DMA request signal B DACK_B 98 INc DMA Acknowledge signal B DRQ_C 4 OUT12t DMA request signal C DACK_ C 18 INc DMA Acknowledge signal C TC 97 INc Terminal Count. When active, this pin indicates termination of a DMA transfer. IRQIN 93 INc Interrupt request input |
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