LV5207LP

No.A0943-8/14

Start and stop conditions

transfer.

When data transfer is not made, both SCL and SDA are in the "H" state.

When SCL = SDA = "H", change of SDA from "H" to "L" enables the start conditions to start access.

When SCL is "H", change of SDA from "L" to "H" enables the stop conditions to stop access.

Data transfer and acknowledgement response

After establishment of start conditions, data transfer is made by one byte (8 bits).

Data transfer enables continuous transfer of any number of bytes.

Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side.

The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set "L" immediately

after fall of the clock pulse at the SCL eighth bit of data transfer to "L".

When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side,

the receive side releases SDA at fall of the SCL ninth clock.

transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction.

Note that only WRITE is valid in LV5207LP.

The 7-bit address is transferred sequentially from MSB and the eight bit is "L" representing WRITE.

In LV5207LP, the slave address is specified as (1110101).

ts2

th2

SCL

SDA

M

S

B

L

S

B

A

C

K

L

S

B

A

C

K

M

S

B

M

S

B

L

S

B

A

C

K

W

1

SCL

SDA

(WRITE)

Start

Slave address

Register address

Data

STOP

110101

0

0

0

1

000

0

0

0

0

0

100

1

th1

ts3

SCL

SDA

Start condition

Stop condition