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W88111AF Datasheet(PDF) 2 Page - Winbond |
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W88111AF Datasheet(HTML) 2 Page - Winbond |
2 / 64 page W88111AF/W88112F Preliminary/Confidential ATAPI CD-ROM Decoder & Controller This specification is subject to change without notice. Publication Release Date: Aug, 1996 - 2 - Preliminary/ Confidential Revision A0.1 STAT3 - Status Register 3 - (read 0Fh) ______________________________________________________22 CTRLW - Control-Write Register - (write 10h) ________________________________________________23 STAT4 - Status Register 4 - (read 10h) ______________________________________________________24 CRTRG - Correction Retry Trigger - (write 11h) ______________________________________________24 MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h) _____________________________________25 MBTC1 - Multi-Block Transfer Control 1 - (read/write 13h) _____________________________________26 ECTRL - Enhanced Control Register - (write 14h) _____________________________________________26 SUBH0 to SUBH3 - Subheader Registers - (read 14h to 17h) ____________________________________27 ASTRG - Automatic Sequence Trigger Register (write 17h) ______________________________________27 ASCTRL - Automatic Sequence Control register - (read/write 18h) ________________________________29 CCTL0 - Clock Control Register 0 - (write 19h) ______________________________________________31 CCTL1 - Clock Control Register 1 - (write 1Ah) _______________________________________________32 VER - Version Register - (read 1Ah) ________________________________________________________32 DSPSL - DSP Selection Register - (write 1Bh) ________________________________________________32 C2BEB - C2 Block Error Byte - (read 1Bh)___________________________________________________33 RACL, RACH, and RACU - RAM Address Counter - (write 1Ch, 1Dh, 2Dh)_________________________33 RAMWR - RAM Write Register - (write 1Eh)__________________________________________________34 RAMRD - RAM Read Register - (read 1Eh) __________________________________________________34 HICTL0 - Host Interface Control Register - (write 1Fh)_________________________________________34 STAT5 - Status Register 5 - (read 1Fh) ______________________________________________________35 HICTL1 - Host Interface Control Register - (write 20h) _________________________________________36 SICTL0 - Subcode Interface Control Register 0 - (write 21h) ____________________________________37 SCIACK - Subcode Interrupt Acknowledge - (write 22h) ________________________________________37 SUBSTA - Subcode Status Register - (read 22h) _______________________________________________38 RAMCF - RAM Configuration Register - (read/write 2Ah)_______________________________________38 MEMCF - Memory Layout Configuration Register - (write 2Bh) __________________________________39 SICTL1 - Subcode Interface Control Register 1 - (write 2Ch) ____________________________________40 MISC0 - Miscellaneous Control Register 0 - (write 2Eh) ________________________________________41 MISS0 - Miscellaneous Status Register 0 - (read 2Eh) __________________________________________42 MISC1 - Miscellaneous Control Register 1 (write 2Fh) _________________________________________43 MISS1 - Miscellaneous Status Register 0 - (read 2Fh) __________________________________________44 ARSTACK - ATAPI Soft Reset Acknowledge (write 30h)_________________________________________45 MISS2 - Miscellaneous Status Register 0 (read 30h)____________________________________________46 |
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