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TQM879006A-PCB Datasheet(PDF) 6 Page - TriQuint Semiconductor |
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TQM879006A-PCB Datasheet(HTML) 6 Page - TriQuint Semiconductor |
6 / 11 page TQM879006A 1.4-2.7GHz ¼ W Digital Variable Gain Amplifier Data Sheet: Rev P 10/19/12 - 6 of 11 - Disclaimer: Subject to change without notice © 2012 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network® Serial Control Interface Serial Control Timing Characteristics (Test conditions: V CC = +5 V, TLEAD=25°C) Parameter Condition Min Max Units Clock Frequency 50% Duty Cycle 10 MHz LE Setup Time, tLESUP after last CLK rising edge 10 ns LE Pulse Width, tLEPW 30 ns SERIN set-up time, tSDSUP before CLK rising edge 10 ns SERIN hold-time, tSDHLD after CLK rising edge 10 ns LE Pulse Spacing tLE LE to LE pulse spacing 630 ns Propagation Delay tPLO LE to Parallel output valid 30 ns Serial Control DC Logic Characteristics (Test conditions: V CC = +5 V, TLEAD=25°C) Parameter Condition Min Max Units Input Low Voltage, VIL 0 0.8 V Input High Voltage, VIH 2.4 Vcc V Input Current, IIH / IIL On SERIN, LE and CLK -10 +10 µA SERIN (MSB in First 6-Bit Word) Control Logic Truth Table MSB 6-Bit Control Word to DSA LSB Gain Relative to Maximum Gain D5 D4 D3 D2 D1 D0 Reference : IL 1 1 1 1 1 1 0 dB 1 1 1 1 1 0 0.5 dB 1 1 1 1 0 1 1 dB 1 1 1 0 1 1 2 dB 1 1 0 1 1 1 4 dB 1 0 1 1 1 1 8 dB 0 1 1 1 1 1 16 dB 0 0 0 0 0 0 31.5 dB Any combination of the possible 64 states will provide a reduction in gain of approximately the sum of the bits selected. Serial Control Interface Timing Diagram CLK is disabled when LE is high SERIN CLK LE D5-D0 MSB-LSB D5-D0 MSB-LSB tSDSUP tSDHLD tLESUP tLEPW tPLO |
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