W986408CH

2M x 8 bit x 4 Banks SDRAM

Revision 1.0

Publication Release Date: March, 1999

- 10 -

Functional Description

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be

followed to guarantee the device being preconditioned to each user specific needs.

During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are

up, an initial pause of 200us is required followed by a precharge of all banks using the precharge command. To prevent data

contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause

period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register.

An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure

proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a

precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode

Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address

input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command

may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page

for Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to

RAS# activate in EDO DRAM. The delay from the Bank Activate command is applied to the first read or write operation can

another Bank Activate command can be issued to it. The minimum time interval between successive Bank Activate commands

Read and Write Access Modes

After a bank has been activated , a read or write cycle can follow. This is accomplished by setting RAS high and CAS low at the

clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation (WE

high), or a write operation (WE low). The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate

command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using

the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access

operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or

between active banks on every clock cycle.