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IS41C16257C Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS41C16257C Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 20 page  IS41C16257C IS41LV16257C 10 Integrated Silicon Solution, Inc. Rev. 00A 04/09/2010 Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-OnlyorCBR)beforeproperdevice operationisassured.TheeightRAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Vih(MIN)andVil(MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVih and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih) in a monotonic manner. 4. If CAS and RAS = Vih,dataoutputisHigh-Z. 5. IfCAS = Vil,dataoutputmaycontaindatafromthelastvalidREADcycle. 6. MeasuredwithaloadequivalenttooneTTLgateand50pF. 7. Assumesthattrcd < trcd(MAX).Iftrcd is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcd exceeds the value shown. 8. Assumesthattrcd ≥ trcd(MAX). 9. If CASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe data output buffer, CAS and RAS must be pulsed for tcp. 10. Operation with the trcd(MAX)limitensuresthattrac(MAX)canbemet.trcd(MAX)isspecifiedasareferencepointonly;iftrcd is greater than the specified trcd(MAX)limit,accesstimeiscontrolledexclusivelybytcac. 11. Operation within the trad(MAX)limitensuresthattrcd(MAX)canbemet.trad(MAX)isspecifiedasareferencepointonly;iftrad is greater than the specified trad (MAX)limit,accesstimeiscontrolledexclusivelybytaa. 12.Eithertrch or trrhmustbesatisfiedforaREADcycle. 13. toff(MAX)definesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVoh or Vol. 14. twcs, trwd, tawd and tcwdarerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftwcs ≥ twcs(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftrwd ≥ trwd(MIN),tawd ≥ tawd(MIN)andtcwd ≥ tcwd(MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vih) is indeterminate. OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled) cycle. 15.Outputparameter(I/O)isreferencedtocorrespondingCASinput,I/O0-I/O7byLCASandI/O8-I/O15byUCAS. 16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a LATEWRITEorREAD-MODIFY-WRITEisnotpossible. 17.WritecommandisdefinedasWE going low. 18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtod and toeh met (OEHIGHduringWRITEcycle)inorderto ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCAS remains LOWandOEistakenbacktoLOWaftertoeh is met. 19.TheI/OsareinopenduringREADcyclesoncetod or toff occur. 20.ThefirstχCASedgetotransitionLOW. 21.ThelastχCASedgetotransitionHIGH. 22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD- MODIFY-WRITEcycles. 23.LastfallingχCAS edge to first rising χCAS edge. 24.LastrisingχCAS edge to next cycle’s last rising χCAS edge. 25.LastrisingχCAS edge to first falling χCAS edge. 26.EachχCAS must meet minimum pulse width. 27.LastχCAStogoLOW. 28.I/Oscontrolled,regardlessUCAS and LCAS. 29.The3nsminimumisaparameterguaranteedbydesign. 30.Enableson-chiprefreshandaddresscounters. |
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