IS43/46DR16128

Integrated Silicon Solution, Inc. – www.issi.com –

8

Rev. B, 09/6/2012

Truth Tables

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

Command Truth Table

Previous

Cycle

Current

Cycle

(Extended) Mode Register

H

H

L

L

L

L

BA

1, 2

Refresh (REF)

H

H

L

L

L

H

X

X

X

X

1

Self Refresh Entry

H

L

L

L

L

H

X

X

X

X

1, 8

H

X

X

X

L

H

H

H

Single Bank Precharge

H

H

L

L

H

L

BA

X

L

X

1, 2

Precharge All Banks

H

H

L

L

H

L

X

X

H

X

1

Bank Activate

H

H

L

L

H

H

BA

1, 2

Write

H

H

L

H

L

L

BA

X

L

Column 1, 2, 3, 10

Write with Auto Precharge

H

H

L

H

L

L

BA

X

H

Column 1, 2, 3, 10

Read

H

H

L

H

L

H

BA

X

L

Column 1, 2, 3, 10

Read with Auto Precharge

H

H

L

H

L

H

BA

X

H

Column 1, 2, 3, 10

No Operation (NOP)

H

X

L

H

H

H

X

X

X

X

1

Device Deselect

H

X

H

X

X

X

X

X

X

X

1

H

X

X

X

L

H

H

H

H

X

X

X

L

H

H

H

1,4

Power Down Exit

L

H

X

X

X

X

1, 4

X

1, 7, 8

Row Address

Power Down Entry

H

L

X

X

X

X

Sel Refresh Exit

L

H

X

X

X

BA2-BA0

A13-A11

A10 A9-A0

Notes

Opcode

Function

CKE

CS#

RAS#

CAS#

WE#

Notes:

1.

All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.

2.

Bank addresses BA0, BA1, and BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

3.

Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" for details.

4.

The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements

5.

The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

6.

“X” means “H or L (but a defined logic level)”

7.

Self refresh exit is asynchronous.

8.

VREF must be maintained during Self Refresh operation.