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AS3588AQ Datasheet(PDF) 2 Page - ams AG |
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AS3588AQ Datasheet(HTML) 2 Page - ams AG |
2 / 15 page Data Sheet AS3588A Rev. 3.1 Page 2 of 15 July 1999 Pinout Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OUT PCM3 . OUT PCM4 OUT PCM2 . OUT PCM 1 . OUT PCM0 . OUT PCM5 OUT PCM6 OUT PCM7 N.C. . CLOCK SYNC INP PCM7 INP PCM6 INP PCM5 INP PCM4 INP PCM3 INP PCM2 INP PCM1 INP PCM0 D7 D6 D5 D4 RD WR CS1 CS2 RESET VSS C/D A1 S1 A2 S2 DR D0 D1 D2 D3 AS3588AP VDD AS3588AQ NC WRN CS1N CS2N RESETN Vss C/DN A1 S1 A2 S2 CLOCK SYNCN INP PCM7 INP PCM6 INP PCM5 INP PCM4 INP PCM3 INP PCM2 INP PCM1 INP PCM0 VDD 1 6 17 28 39 Figure 2: Pinout 40 pin DIP and 44 pin QFP Pin Description DIP QFP Type Symbol Description 1 - 4 40 - 43 OP OUTPCM3 to OUTPCM0 PCM Outputs 3 to 0. These are open drain outputs for four primary rate PCM output streams. 5 44, 12, 17, 33, 39 - N.C. Unused Pin 6 1 IP CLOCK Master Clock Input This signal is the timing reference for all internal operations. The PCM bit cell boundaries lie on the alternate rising edges of this clock. 7 2 IP SYNC Synchronization Input This is an edge sensitive input for frame synchronization in the PCM bit stream with a typical repetition rate of 8 kHz. The rising edge determines the start of a new frame. 8 - 15 3 - 10 IP INPPCM7 to INPPCM0 PCM Inputs 7 to 0 These are the inputs for primary rate PCM input streams 16 11 Power VDD Positive Supply Voltage 17 - 24 13 - 16, 18 - 21 I/O D7 to DO Data Bus I/O Port. These are the bi-directional data pins to the microprocessor interface. Only 5 bits are used when data is written into AS3588A (D4 to D0) 25 22 OP DR Data Ready Output. This active high signal goes low for signalling purposes |
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