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AS8201 Datasheet(PDF) 9 Page - ams AG |
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AS8201 Datasheet(HTML) 9 Page - ams AG |
9 / 13 page TTP/C-C1 Communications Controller Data Sheet AS8201 Rev. NC, October 1999 Page 9 of 13 Austria Mikro Systeme International AG microtick t ct ram_web ram_ceb t ce ram_address XXX t a ram_data XXXX t rwct address stable data stable Figure 4: Write Cycle Timing Addresses, data and RAM_WEB have to be stable before the falling edge of RAM_CEB. RAM_CEB has to be applied for 2 microticks. Addresses, data, and RAM_WEB have to be applied for 3 microticks. Parameter Symbol Min Typ Max controller cycle time tct 50ns duration of chip enable tce 87.5ns 100ns 112.5ns address time ta 137.5ns 150ns 162.5ns data valid time tdv 300ns read write cycle time trwct 300ns Table 3: Host Interface Timing Reset and Oscillator Pin Name mode width Comment XIN0 in 1 controller oscillator input XENA0 in 1 controller clock enable XOUT0 out 1 controller oscillator output XIN1 in 1 bus guardian oscillator input XOUT1 out 1 bus guardian oscillator output XENA1 in 1 bus guardian clock enable RESETB in 1 external reset MICROTICK out 1 controller clock (inverted) Table 4: Reset and Oscillator Ports External Reset Signal To issue a reset of the chip the RESETB port has to be driven low for at least 200µs. After power-up the reset must overlap the build-up time of the oscillator circuit. |
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