V-Data

VDS6608A4A

AC Characteristics

-7.5

Parameter

Symbol

Min Max

Unit Note

/CAS Latency = 3

tCK3

7.5

System clock

Cycle time

/CAS Latency = 2

tCK2

10

1000 ns

Clock high pulse width

tCHW

2.5

-

ns

1

Clock low pulse width

tCLW

2.5

-

ns

1

/CAS Latency = 3

tAC3

-

5.4

Access time

form clock

/CAS Latency = 2

tAC2

-

6

ns

2

Operation

tRC

65

-

/RAS cycle

time

Auto Refresh

tRRC

65

-

ns

/RAS to /CAS delay

tRCD

20

-

ns

/RAS active time

tRAS

45

100

ns

/RAS precharge time

tRP

20

-

ns

/RAS to /RAS bank active delay

tRRD

15

-

ns

/CAS to /CAS delay

tCCD

1

-

CLK

Data – in active command

tDAL

4

-

CLK

Data – out hold time

tOH

3

-

ns

Address setup time

tAS

1.5

-

ns

1

Address hold time

tAH

1

-

ns

1

CKE setup time

tCKS

1.5

-

ns

1

CKE hold time

tCKH

1

-

ns

1

Command setup time

tCS

1.5

-

ns

1

Command hold time

tCH

1

-

ns

1

CLK to data output in low Z-time

tOLZ

1.5

-

ns

MRS to new command

tMRD

1

-

CLK

Power down exit time

tPDE

1

-

CLK

Self refresh exit time

tSRE

1

-

CLK

3

Refresh time

tREF

64

-

ms

Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.

2. Access times to be measured with input signals of 1v / ns edge rate.

3.A new command can be given tRRC after self refresh exit.

Rev 1 April, 2001

6