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ENA2098 Datasheet(PDF) 10 Page - Sanyo Semicon Device |
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ENA2098 Datasheet(HTML) 10 Page - Sanyo Semicon Device |
10 / 23 page LE25U40CMC No.A2098-10/23 BP0, BP1, BP2, TB (Bits 2, 3, 4, 5) Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions". BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address area or lower-order address area. Table 5 Protect Level Setting Conditions Protect Level Status Register Bits Protected Area TB BP2 BP1 BP0 0 (Whole area unprotected) X 0 0 0 None T1 (Upper side 1/8 protected) 0 0 0 1 07FFFFh to 070000h T2 (Upper side 1/4 protected) 0 0 1 0 07FFFFh to 060000h T3 (Upper side 1/2 protected) 0 0 1 1 07FFFFh to 040000h B1 (Lower side 1/8 protected) 1 1 0 1 00FFFFh to 000000h B2 (Lower side 1/4 protected) 1 1 1 0 01FFFFh to 000000h B3 (Lower side 1/2 protected) 1 1 1 1 03FFFFh to 000000h 4 (Whole area protected) X 1 X X 07FFFFh to 000000h * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting conditions". Table 6 SRWP Setting Conditions WP Pin SRWP Status Register Protect State 0 0 Unprotected 1 Protected 1 0 Unprotected 1 Unprotected Bit 6 are reserved bits, and have no significance. |
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