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AD14160 Datasheet(PDF) 4 Page - Analog Devices |
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AD14160 Datasheet(HTML) 4 Page - Analog Devices |
4 / 52 page AD14160/AD14160L –4– REV. A Shared Memory Multiprocessing The AD14160/AD14160L takes advantage of the powerful multiprocessing features built into the SHARC. The SHARCs are connected to maximize the performance of this cluster-of-four architecture, and still allow for off-module expansion. The AD14160/AD14160L in itself is a complete shared memory multiprocessing system, as shown in Figure 3. The unified ad- dress space of the SHARCs allows direct interprocessor ac- cesses of each SHARCs’ internal memory. In other words, each SHARC can directly access the internal memory and IOP registers of each of the other SHARCs by simply reading or writing to the appropriate address in multi-processor memory space (see Fig- ure 2)—this is called a direct read or direct write. Bus arbitration is accomplished with the on-SHARC arbitration logic. Each SHARC has a unique ID, and drives the Bus-Request (BR) line corresponding to its ID, while monitoring all others. BR1–BR4 are used within the AD14160/AD14160L, while BR5 and BR6 can be used for expansion. All bus requests (BR1–BR6) are included in the module I/O. Two different priority schemes, fixed and rotating, are available to resolve competing bus requests. The RPBA pin selects which scheme is used: when RPBA is high, rotating priority bus arbitra- tion is selected, and when RPBA is low, fixed priority is selected. Table I. Rotating Priority Arbitration Example Hardware Processor IDs Cycle ID1 ID2 ID3 ID4 ID5 ID6 1M 1 2 BR 3 4 5 Initial Priority Assignments 2 4 5 BR M-BR 1 2 3 3 4 5 BR M 1 2 3 4 5 BR M 1 2 3 4 BR 51 BR 2 3 4 5 M Final Priority Assignments NOTES 1–5 = Assigned Priority. M = Bus Mastership (in that cycle). BR = Requesting Bus Mastership with BRx. Bus mastership is passed from one SHARC to another during a bus transition cycle. A bus transition cycle only occurs when the current bus master deasserts its BR line and one of the slave SHARCs asserts its BR line. The bus master can therefore re- tain bus mastership by keeping its BR line asserted. When the bus master deasserts its BR line, and no other BR line is as- serted, then the master will not lose any bus cycles. When more than one SHARC asserts its BR line, the SHARC with the highest priority request becomes bus master on the following cycle. Each SHARC observes all of the BR lines, and therefore tracks when a bus transition cycle has occurred, and which processor has become the new bus master. Master processor changeover incurs only one cycle of overhead. An example bus transition sequence is shown in Table I. Bus locking is possible, allowing indivisible read-modify-write sequences for semaphores. In either the fixed or rotating priority scheme, it is also possible to limit the number of cycles the master can control the bus. The AD14160/AD14160L also provides the option of using the Core Priority Access (CPA) mode of the SHARC. Using the CPA signal allows external bus accesses by the core processor of a slave SHARC to take priority over ongoing DMA transfers. Also, each SHARC can broadcast write to all other SHARCs simultaneously, allowing the implemen- tation of reflective semaphores. The bus master can communicate with slave SHARCs by writ- ing messages to their internal IOP registers. The MSRG0– MSRG7 registers are general-purpose registers that can be used for convenient message passing, semaphores and resource shar- ing between the SHARCs. For message passing, the master communicates with a slave by writing and/or reading any of the eight message registers on the slave. For vector interrupts, the master can issue a vector interrupt to a slave by writing the address of an interrupt service routine to the slave’s VIRPT register. This causes an immediate high priority interrupt on the slave which, when serviced, will cause it to branch to the speci- fied service routine. Off-Module Memory and Peripherals Interface The AD14160/AD14160L’s external port provides the interface to off-module memory and peripherals (see Figure 5). This port consists of the complete external port bus of the SHARC, bused together in common among the four SHARCs. The 4-gigaword off-module address space is included in the AD14160/AD14160L’s unified address space. Addressing of external memory devices is facilitated by each SHARC inter- nally decoding the high order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The AD14160/ AD14160L also supports programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements. Link Port I/O Each individual SHARC features six 4-bit link ports that facili- tate SHARC-to-SHARC communication and external I/O inter- facing. Each link port can be configured for either 1 × or 2× operation, allowing each to transfer either 4 or 8 bits per cycle. The link ports can operate independently and simultaneously, with a maximum bandwidth of 40 MBytes/s each, or a total of 240 MBytes/s per SHARC. The AD14160/AD14160L provides additional link port I/O beyond that of the AD14060. Internally, two links from each SHARC form a ring connection among the four. The remaining four link ports from each SHARC are brought out indepen- dently from each SHARC. A maximum of 640 MBytes/s link port bandwidth is then available off of the AD14160/AD14160L. The link port connections are detailed in Figure 4. SHARC_A SHARC_B SHARC_D SHARC_C 1 2 4 3 1 2 4 3 55 55 0 0 0 0 1 2 4 3 1 2 4 3 Figure 4. Link Port Connections |
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