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AD1862N Datasheet(PDF) 8 Page - Analog Devices |
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AD1862N Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page AD1862 –8– REV. A OPTIONAL TRIM ADJUSTMENT The AD1862 includes an external midscale adjust feature. Should an application require improved distortion performance under small and very small signal amplitudes (–60 dB and lower), an adjustment is possible. Two resistors and one poten- tiometer form the adjustment network. Figure 11 illustrates the correct configuration of the external components. Analog Devices recommends that this adjustment be performed with –60 dB signal amplitudes or lower. Minor performance im- provement is achieved with larger signal amplitudes such as –20 dB. Almost no improvement is possible when this adjust- ment is performed with 0 dB signal amplitudes. 470k Ω 470k Ω 100k Ω AD1862 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 – 12V Figure 11. External Midscale Adjust DIGITAL CIRCUIT CONSIDERATIONS INPUT DATA Data is transmitted to the AD1862 in a bit stream composed of 20-bit words with a serial, 2s complement, MSB first format. Three signals must be present to achieve proper operation. They are the data, clock and latch enable signals. Input data bits are clocked into the input register on the rising edge of the clock signal (CLK). The LSB is clocked in on the 20th clock pulse. When all data bits are loaded, a low going latch enable (LE) pulse updates the DAC input. Figure 12a illustrates the general signal requirements for data transfer for the AD1862. MSB WORD n LSB MSB WORD n+1 DATA CLOCK LATCH ENABLE Figure 12a. Input Data TIMING Figure 12b illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished success- fully. The input pins of the AD1862 are both TTL and 5 V CMOS compatible, independent of the power supplies used in the application. The input requirements illustrated in Figure 12b are compatible with the data outputs provided by popular digital interpolation filter chips used in digital audio playback systems. The AD1862 input clock will run at 17 MHz allowing data to be transferred at a rate of 16 × F S. Of course, it will also function at slower rates such as 2 ×, 4 × or 8 × F S. >15ns >15ns BITS CLOCKED TO SHIFT REGISTER CLK > 60ns >15ns >25ns >25ns DATA LATCH ENABLE (LE) >60ns >40ns INTERNAL DAC INPUT REGISTER UPDATED WITH 20 MOST RECENT BITS 2nd BIT LSB (20th BIT) WORD NEXT >40ns >40ns MSB 1st BIT Figure 12b. Timing Requirements |
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