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AD1864N-K Datasheet(PDF) 7 Page - Analog Devices |
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AD1864N-K Datasheet(HTML) 7 Page - Analog Devices |
7 / 12 page AD1864 –7– REV. A CURRENT OUTPUT MODE One or both channels of the ADl864 can be operated in current output mode. IOUT can be used to directly drive an external current-to-voltage (I-V) converter. The internal feedback resistor, RF, can still be used in the feedback path of the external I-V converter, thus assuring that RF tracks the DAC over time and temperature. Of course, the AD1864 can also be used in voltage output mode utilizing the onboard I-V converter. VOLTAGE OUTPUT MODES As shown in the ADl864 block diagram, each channel of the ADl864 is complete with an I-V converter and a feedback resistor. These can be connected externally to provide direct voltage output from one or both AD1864 channels. Figure 7 shows these connections. IOUT is connected to the summing junction, SJ. VOUT is connected to the feedback resistor, RF. This implementation results in the L S B M S B M S B DL DR LL LR CLK L S B Figure 9. Control Signals >15ns >60ns >40ns >40ns >30ns CLK MSB 1st BIT 2nd BIT LSB (18th BIT) NEXT WORD >80ns INTERNAL DAC REGISTER UPDATED WITH 18 MOST RECENT BITS >15ns >15ns >40ns LL/LR DL/DR BITS CLOCKED TOSHIFT REGISTER >30ns Figure 10. Timing Diagram INPUT DATA Data is transmitted to the AD1864 in a bit stream composed of 18-bit words with a serial, twos complement, MSB first format. Data Left (DL) and Data Right (DR) are the serial inputs for the left and right DACs, respectively. Similarly, Latch Left (LL) and Latch Right (LR) update the left and right DACs. The falling edges of LL and LR cause the last 18 bits clocked into the Serial Registers to be shifted into the DACs, thereby updating the DAC outputs. Left and Right channels share the Clock (CLK) signal. Data is clocked into the input registers on the rising edge of CLK. Figure 9 illustrates the general signal requirements for data transfer for the AD1864. lowest possible component count and achieves the performance shown on the specifications page while operating at 8 × F S. TIMING Figure 10 illustrates the specific timing requirements that must be met in order for the data transfer to be properly accomplished. The input pins of the AD1864 are both TTL and 5 V CMOS compatible. The minimum clock rate of the AD1864 is at least 12.7 MHz. This clock rate allows data transfer rates of 2 ×, 4×, 8× and 16 × F S (where FS equals 44.1 kHz). The applications section of this data sheet contains additional guidelines for using the AD1864. |
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