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AD1896AYRSRL Datasheet(PDF) 3 Page - Analog Devices

Part # AD1896AYRSRL
Description  192 kHz Stereo Asynchronous Sample Rate Converter
Download  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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REV. A
–3–
AD1896
DIGITAL TIMING (–40 C < TA < +105 C, VDD_CORE = 3.3 V
5%, VDD_IO = 5.0 V
10%)
Parameter
1
Min
Typ
Max
Unit
tMCLKI
MCLK_I Period
33.3
ns
fMCLK
MCLK_I Frequency
30.0
2, 3
MHz
tMPWH
MCLK_I Pulsewidth High
9
ns
tMPWL
MCLK_I Pulsewidth Low
12
ns
Input Serial Port Timing
tLRIS
LRCLK_I Setup to SCLK_I
8
ns
tSIH
SCLK_I Pulsewidth High
8
ns
tSIL
SCLK_I Pulsewidth Low
8
ns
tDIS
SDATA_I Setup to SCLK_I Rising Edge
8
ns
tDIH
SDATA_I Hold from SCLK_I Rising Edge
3
ns
Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge
(Serial Input Port MASTER)
12
ns
Propagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge
(Serial Input Port MASTER)
12
ns
Output Serial Port Timing
tTDMS
TDM_IN Setup to SCLK_O Falling Edge
3
ns
tTDMH
TDM_IN Hold from SCLK_O Falling Edge
3
ns
tDOPD
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
20
ns
tDOH
SDATA_O Hold from SCLK_O
3
ns
tLROS
LRCLK_O Setup to SCLK_O (TDM Mode Only)
5
ns
tLROH
LRCLK_O Hold from SCLK_O (TDM Mode Only)
3
ns
tSOH
SCLK_O Pulsewidth High
10
ns
tSOL
SCLK_O Pulsewidth Low
5
ns
tRSTL
RESET Pulsewidth Low
200
ns
Propagation Delay from MCLK_I Rising Edge to SCLK_O Rising Edge
(Serial Output Port MASTER)
12
ns
Propagation Delay from MCLK_I Rising Edge to LRCLK_O Rising Edge
(Serial Output Port MASTER)
12
ns
NOTES
1Refer to Timing Diagrams section.
2The maximum possible sample rate is: FS
MAX = fMCLK /138.
3f
MCLK of up to 34 MHz is possible under the following conditions: 0
∞C < TA < 70∞C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.


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