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AD28MSP02BR Datasheet(PDF) 7 Page - Analog Devices |
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AD28MSP02BR Datasheet(HTML) 7 Page - Analog Devices |
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7 / 20 page  AD28msp02 REV. 0 –7– Table III. Control Word Read Format Read Request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 00 0 0 0 0 0 000 Read Ready 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 00 0 0 0 0 0 000 Control Register Reads To read the control register, the host processor must transfer two control words. For each transfer, the DATA/CNTRL pin must be low when SDIFS is asserted. If the MSB of the bit stream is high, the SPORT recognizes the incoming serial data as a request for control information. The protocol for reading the control register is as follows: 1. The host processor sends a “Read Request” control word to the AD28msp02. Since the MSB of this control word is high, the SPORT recognized the incoming serial data as a read re- quest and does not overwrite the control register. 2. When the AD28msp02 receives the read request, it finishes any data transfers in progress and waits for a “Read Ready” control word. 3. The host processor then transfers a “Read Ready” control word to the AD28msp02. Upon receiving this control word, the AD28msp02 transfers the control register contents to the host processor via the SPORT. 4. When the SPORT completes the control register transfer, it immediately resumes transmitting data at an 8 kHz rate. This scheme allows any data transfers in progress to be com- pleted and resolves any ambiguities between data and control words. The format for the read control words is shown in Table III. DESIGN CONSIDERATIONS Analog Input The analog input signal to the AD28msp02 must be ac-coupled. Figure 7 shows the recommended input circuit for the AD28msp02’s analog input pin (either VINNORM or VINAUX). The circuit of Figure 7 implements a first-order low-pass filter with a 3 dB point at 20 kHz; this is the only filter that must be implemented external to the AD28msp02 to prevent aliasing of the sampled signal. Since the AD28msp02’s ADC uses a highly oversampled approach that transfers the bulk of the anti-aliasing filtering into the digital domain, the off-chip anti-aliasing filter need only be of low order. In the circuit shown in Figure 7, scaling of the analog input is achieved by the resistors RIN and RFB. The input signal gain, –RFB/RIN, can be adjusted from –12 dB to +26 dB by varying the values of these resistors. The AD28msp02’s on-chip 20 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by Bit 0 (IPS) of the control register. Total gain must be configured to ensure that a full-scale input signal (at CIN in Figure 7) produces a sig- nal level at the input to the sigma-delta modulator of the ADC that does not exceed VINMAX, which is specified under “Analog Interface Electrical Characteristics.” If the total gain is increased above unity, signal-to-noise (SNR + THD) performance will not meet the listed specifications. MUX VOLTAGE REFERENCE VFB VFB VIN AD28msp02 VIN NORM AUX NORM AUX CFB CIN R IN RFB INPUT SIGNAL Figure 7. Recommended Analog Input Circuit The dc biasing of the analog input signal is accomplished with an on-chip voltage reference which nominally equals 2.5 V. The input signal must be ac-coupled with an external coupling ca- pacitor (CIN). CIN and RIN should be chosen to ensure a cou- pling corner frequency of 30 Hz. CIN should be 0.1 µF or larger. |
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