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A3944 Datasheet(PDF) 10 Page - Allegro MicroSystems |
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A3944 Datasheet(HTML) 10 Page - Allegro MicroSystems |
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10 / 31 page  Automotive, Low Side FET Pre-Driver A3944 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com high, in other words the logical OR of the INx input and the Gx bit for each channel x. If the GATx output is to be controlled by the serial interface, then the corresponding INx logic input should be held low. Internal pull-down resistors from each INx terminal to GND ensure that any unconnected input will be pulled low. Conversely, if the GATx output is to be controlled by the INx logic input, then the corresponding Gx bit in the control register should be set to 0, which is its default power-on and reset state. Gate Drive Output Each gate drive output is designed to provide symmetrical charge current from the VDR supply terminal and discharge current to the GND return terminal. The maximum source and sink imped- ance provides peak charge and discharge currents of at least 50 mA when connected directly to the gate of the external FET. This current can be limited, in order to limit the FET turn-on switching speed, by using a resistor between the GATx output and the gate of the FET. Although the GATx drive is designed to be symmetrical, the actual drive performance will be affected by the FET parameters and the resistance between the GATx output and the gate of the FET. The VDR supply is used only to supply the GATx output. The voltage at VDR can therefore be varied to provide voltage limited drive to the FET gate. Undervoltage detection is not provided for this supply. Reset Function If RESETN is held low for more than the minimum reset pulse width, then all registers are reset to their power-on state, and all GATx outputs are held low. Any latched channel faults and cor- responding bits in the fault register are reset, the logic reset (LR) bit is set, and the UV and OT bits reflect the status of the under- voltage and overtemperature detectors. The RESETN input uses a glitch filter to reduce the susceptibility to transients and noise on the RESETN input. This glitch filter is guaranteed to ignore any pulses shorter than the minimum RESETN glitch filter time, tRGF. Channel Fault Diagnostics All channel faults are determined by monitoring the voltage at the drain of the external FET through the DRNx terminal. Each chan- nel has independent bias current generators, programmable fault comparators, fault decode logic, and programmable fault timers. The serial interface provides a dedicated fault configuration reg- ister for each channel to select these features and thresholds per channel. A single fault mask register provides a fault mask bit for each channel. Fault detection is disabled when RESETN is low or when the fault mask bit is set. Fault reporting through the serial interface is fully described in the Serial Interface section below. A short to battery (short across the load to the load supply) can be detected when the channel is active, GATx is high, and the FET is on (on-state). A short to battery fault always attempts to protect the FET by pulling GATx low. A short to ground or open load can be detected when GATx is low and the FET is off (off-state). A short to ground fault or open load fault does not interfere with the operation of the GATx output. Each channel fault detected is latched as a fault state, and remains latched until the diagnostic circuits can determine that the fault has been removed for that channel. This determination can only occur at the end of a fault blank time. For short to battery this is at the end of the on-state fault blank time following a transition from off to on. For a short to ground or open load this is at the end of the off-state fault blank time following a transition from on to off. When a fault is detected, a dedicated bit in one of the two fault registers is set for each fault on each channel. This requires 3 bits per channel over 6 channels or 18 fault bits in total. The fault bits in the fault registers remain latched until the first serial transfer after the associated fault state has been reset. All latched fault states and all latched channel fault bits can also be cleared either by a power-on reset or by taking the RESETN terminal low. Practical limits for load resistance, and voltage conditions to provide effective determination of the load status, are discussed in the Applications Information section below. Note that each DRNx terminal has an internal Zener clamp which limits the voltage at the terminal to VDCL. If the voltage at the drain of the FET is likely to be higher than VDCL, even dur- ing a transient, then a current limit resistor, RDx, must be added |
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