REV. 0

AD5302/AD5312/AD5322

–11–

SERIAL INTERFACE

The AD5302/AD5312/AD5322 are controlled over a versatile,

3-wire serial interface, which operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE and DSP

interface standards.

Input Shift Register

The input shift register is 16 bits wide (see Figures 28–30 below).

Data is loaded into the device as a 16-bit word under the con-

trol of a serial clock input, SCLK. The timing diagram for this

operation is shown in Figure 1. The 16-bit word consists of four

control bits followed by 8, 10 or 12 bits of DAC data, depend-

ing on the device type. The first bit loaded is the MSB (Bit 15),

which determines whether the data is for DAC A or DAC B. Bit

14 determines if the reference input will be buffered or unbuf-

fered. Bits 13 and 12 control the operating mode of the DAC.

Table I. Control Bits

Power-On

Bit

Name

Function

Default

15

A/B

0: Data Written to DAC A

N/A

1: Data Written to DAC B

14

BUF

0: Reference Is Unbuffered

0

1: Reference Is Buffered

13

PD1

Mode Bit

0

12

PD0

Mode Bit

0

A/B BUF PD1 PD0 D7

D6

D5

D4

D3

D2

D1

D0

XXXX

DB0 (LSB)

DB15 (MSB)

DATA BITS

Figure 28. AD5302 Input Shift Register Contents

A/B BUF PD1 PD0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

DB0 (LSB)

DB15 (MSB)

DATA BITS

Figure 29. AD5312 Input Shift Register Contents

A/B BUF PD1 PD0 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DB0 (LSB)

DB15 (MSB)

DATA BITS

Figure 30. AD5322 Input Shift Register Contents

The remaining bits are DAC data bits, starting with the MSB

and ending with the LSB. The AD5322 uses all 12 bits of DAC

data, the AD5312 uses 10 bits and ignores the 2 LSBs. The

AD5302 uses eight bits and ignores the last four bits. The data

format is straight binary, with all zeroes corresponding to

0 V output, and all ones corresponding to full-scale output

The

SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can only be trans-

ferred into the device while

SYNC is low. To start the serial

data transfer,

SYNC should be taken low observing the mini-

mum

SYNC to SCLK active edge setup time, t

goes low, serial data will be shifted into the device’s input shift

register on the falling edges of SCLK for 16 clock pulses. Any

data and clock pulses after the 16th will be ignored, and no

further serial data transfer will occur until

SYNC is taken high

and low again.

SYNC may be taken high after the falling edge of the 16th

SCLK pulse, observing the minimum SCLK falling edge to

SYNC rising edge time, t

After the end of serial data transfer, data will automatically be

transferred from the input shift register to the input register of

the selected DAC. If

SYNC is taken high before the 16th falling

edge of SCLK, the data transfer will be aborted and the input

registers will not be updated.

When data has been transferred into both input registers, the

DAC registers of both DACs may be simultaneously updated,

by taking

LDAC low.

Low Power Serial Interface

To reduce the power consumption of the device even further,

the interface only powers up fully when the device is being writ-

ten to. As soon as the 16-bit control word has been written to

the part, the SCLK and DIN input buffers are powered down.

They only power-up again following a falling edge of

SYNC.

Double-Buffered Interface

The AD5302/AD5312/AD5322 DACs all have double-buffered

interfaces consisting of two banks of registers—input registers

and DAC registers. The input register is connected directly to

the input shift register and the digital code is transferred to the

relevant input register on completion of a valid write sequence.

The DAC register contains the digital code used by the resistor

string.

Access to the DAC register is controlled by the

LDAC function.

When

LDAC is high, the DAC register is latched and the input

register may change state without affecting the contents of the

DAC register. However, when

LDAC is brought low, the DAC

register becomes transparent and the contents of the input regis-

ter are transferred to it.

This is useful if the user requires simultaneous updating of both

DAC outputs. The user may write to both input registers indi-

vidually and then, by pulsing the

LDAC input low, both outputs

will update simultaneously.

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that

LDAC was brought low. Normally, when

LDAC is brought low, the DAC registers are filled with the

contents of the input registers. In the case of the AD5302/AD5312/

AD5322, the part will only update the DAC register if the input

register has been changed since the last time the DAC register

was updated thereby removing unnecessary digital crosstalk.