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A8601 Datasheet(PDF) 5 Page - Allegro MicroSystems |
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A8601 Datasheet(HTML) 5 Page - Allegro MicroSystems |
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5 / 32 page  Multiple-Output Regulator for Automotive LCD Displays A8601 5 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Pin-out Diagram Terminal List Table Number Name Function 1 GATE Gate driver for input disconnect P-MOSFET 2 INS High-side sense for input overcurrent detection 3 VIN Input supply voltage (4.0 to 5.5 V) for the IC 4 DVDD Output from internal LDO (item 1 in Functional Block Diagram) powered by VIN 5 FB1 (DVDD) Connect to resistor divider network to set DVDD 6 COMP Compensation pin, connect to external COMP capacitor 7 VINAMP Control voltage from external microprocessor 8 VCOM Output from operational amplifier (item 5 in Functional Block Diagram), controlled by VINAMP 9 GNDVCOM Ground reference for VCOM 10 FSET_SYNC Input for synchronizing boost and charge pump signals switching frequency to external clock signal; alternatively, it can be connected to an external resistor to set the switching frequency 11 BIAS Output from internal 3.6 V bias regulator; connect to GND via 0.1 μF ceramic capacitor 12 ¯F¯¯A¯¯¯U¯¯L¯¯T¯ Open-drain output, pulls low in error condition 13 EN1 Enable pin for DVDD output; system can only be enabled after VVIN is above UVLO level (refer to Startup Timing Diagram) 14 EN2 Enable pin for the voltage outputs other than DVDD; it can be activated only after VVIN is above UVLO and EN1 = high. GATE INS VIN DVDD FB1 COMP VINAMP VCOM GNDVCOM FSET_SYNC BIAS FAULT EN1 EN2 SW PGND OUT AVDD FB2 CP11 CP12 VGH FB4 CP21 CP22 VGL FB3 AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PAD Number Name Function 15 AGND Analog GND reference for signals; connect to ground plane 16 FB3 (VGL) Connect to resistor divider network to set VVGL 17 VGL Inverted charge pump output (item 3 in Functional Block Diagram) 18 CP22 Capacitor terminal for inverted charge pump (item 3 in Functional Block Diagram); refer to Negative Charge Pump section for usage 19 CP21 Capacitor terminal for inverted charge pump (item 3 in Functional Block Diagram) 20 FB4 (VGH) Connect to resistor divider network to set VVGH 21 VGH 2x charge pump (item 4 in Functional Block Diagram) output 22 CP12 Capacitor terminals for charge pump (item 4 in Functional Block Diagram) 23 CP11 24 FB2 (AVDD) Connect to external resistor network to set VAVDD 25 AVDD Output from internal LDO (item 2 in Functional Block Diagram) powered by VOUT 26 OUT Connect to boost output for internal LDO and charge pump regulators 27 PGND Power ground for internal boost switch; connect this pin to ground terminal of output ceramic capacitor(s) 28 SW Boost converter switch node – PAD Exposed pad (substrate of IC); solder to GND plane for better thermal conduction |
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