Photoflash Capacitor Charger

with Programmable Current Limit and IGBT Driver

A8835

11

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Minimize parasitic capacitors with careful layout. The center pad

between R1 and R2 should be routed away from any GND and

other traces. Avoid placing the GND plane directly underneath

the center pad.

Place R1 and R2 as close as possible in a straight line as shown in

figure 18.

D1

+

R1

R2

R3

COUT

CP1

CP2

A8835

FB

SW

Figure 17. Equivalent circuit with parasitic capacitors across feedback

divider.

Figure 18. Recommended layout for feedback divider.

R1

R2

R3

FB

GND

Do not locate areas

of the GND plane

underneath this zone