Electronic Components Datasheet Search |
|
AD568SQ Datasheet(PDF) 11 Page - Analog Devices |
|
AD568SQ Datasheet(HTML) 11 Page - Analog Devices |
11 / 14 page AD568 REV. A –11– 5V DIGITAL GROUND PLANE CLOCK ANALOG GROUND PLANE +15V –15V OUTPUT 5V INPUT WORDS AD568 SETTLING/GLITCH EVALUATION BOARD Component Side ANALOG +5V +5V ANALOG VCC ANALOG VEE Foil Side Figure 18. Printed Circuit Board Layout High-Speed Interconnect and Routing It is essential that care be taken in the signal and power ground circuits to avoid inducing extraneous voltage drops in the signal ground paths. It is suggested that all connections be short and direct, and as physically close to the package as possible, so that the length of any conduction path shared by external compo- nents will be minimized. When runs exceed an inch or so in length, some type of termination resistor may be required. The necessity and value of this resistor will be dependent upon the logic family used. For maximum ac performance, the DAC should be mounted di- rectly to the circuit board; sockets should not be used as they in- troduce unwanted capacitive coupling between adjacent pins of the device. Applications 1 s, 12-BIT SUCCESSIVE APPROXIMATION A/D CONVERTER The AD568’s unique combination of high speed and true 12-bit accuracy can be used to construct a 12-bit SAR-type A/D con- verter with a sub- µs conversion time. Figure 19 shows the con- figuration used for this application. A negative analog input voltage is converted into current and brought into a summing junction with the DAC current. This summing junction is bidirectionally clamped with two Schottky diodes to limit its voltage excursion from ground. This voltage is differentially am- plified and passed to a high-speed comparator. The comparator output is latched and fed back to the successive approximation register, which is then clocked to generated the next set of codes for the DAC. 13 16 15 14 24 23 22 21 20 19 18 17 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT 12 11 10 9 8 1 2 3 4 7 6 5 DAC AD568 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE 100pF 1k +5V NC NC 4 7 6 5 21 20 19 18 17 16 9 8 Q11 Q10 Q9 Q8 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 11 3 14 1 13 24 12 2 23 22 15 10 VCC GND D0 Q 11 NC NC CP E S CC D NC +5V PARALLEL DATA OUT SAR 2504 0.01µF 1k 620 620 2.5k VI 0 TO –10.24V N +5V –5V –5V 1k 150 Q1 Q2 Q3 D1 D2 27k –15V 1 2 3 4 8 7 6 5 V+ +IN V– –IN OUT OUT LCH GND COMPARATOR LT1016 D3 IN4148 CONVERSION COMPLETE START COMVERT CHIP ENABLE 150k Ω +5V INVERTER 74HC04 15k Ω 150k Ω Q4 Q5 Figure 19. AD568 1 µs Successive Approximation A/D Application |
Similar Part No. - AD568SQ |
|
Similar Description - AD568SQ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |