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MJW16110 Datasheet(PDF) 6 Page - Motorola, Inc |
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MJW16110 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 10 page MJ16110 MJW16110 6 Motorola Bipolar Power Transistor Device Data DYNAMIC SATURATION VOLTAGE For bipolar power transistors low DC saturation voltages are achieved by conductivity modulating the collector region. Since conductivity modulation takes a finite amount of time, DC saturation voltages are not achieved instantly at turn–on. In bridge circuits, two transistor forward converters, and two transistor flyback converters dynamic saturation characteris- tics are responsible for the bulk of dynamic losses. The MJ16110 has been designed specifically to minimize these losses. Performance is roughly four times better than the original version of MJ16010. From a measurement point of view, dynamic saturation voltage is defined as collector–emitter voltage at a specific point in time after IB1 has been applied, where t = 0 is the 90% point on the IB1 rise time waveform, This definition is il- lustrated in Figure 11. Performance data was taken in the cir- cuit that is shown in Figure 13. The 24 volt rail allows a Tektronix 2445 or equivalent scope to operate at 1 volt per division without input amplifier saturation. Dynamic saturation performance is illustrated in Figure 12. The MJ16110 reaches DC saturation levels in approximately 2 µs, provided that sufficient base drive is provided. The de- pendence of dynamic saturation voltage upon base drive suggests a spike of IB1 at turn–on to minimize dynamic satu- ration losses, and also avoid overdrive at turn–off. However, in order to simulate worst case conditions the guaranteed dy- namic saturation limits in this data sheet are specified with a constant level of IB1. + 24 1 k 1 k 10 k 0.1 µF 0.01 µF 100 pF U1 MC1455 (OSCILLATOR) 1N5314 Q1 1N4111 MJ11012 100 µF 100 Ω 1 W 2.4 Ω 20 W 0.01 µF Q4 IRFD9120 Q5 MTM8P08 2.4 mH 1N5831 10 µF I C I B V CE MUR405 MUR405 47 Ω 1 W 500 Ω Q2 Q3 IRFD113 0.01 µF 0.01 µF IRFD9123 1N914 10 k 1.8 k Q6 MTP25N06 4 8 7 6 2 1 5 3 4 8 2 3 7 6 1 5 Figure 13. Dynamic Saturation Test Circuit 20 0 200 14 10 16 8 4 2 400 600 12 18 6 50 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) 0.01 20 5 1 10 0.5 0.2 0.1 0.02 100 500 REGION II — EXPANDED FBSOA USING MUR870 ULTRA-FAST RECTIFIER, SEE FIGURE 16 TC = 25°C 10 µs 1 ms dc 100 ns 0 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) Figure 14. Forward Bias Safe Operating Area IC/IB1 = 5 TJ ≤ 100°C MJW16110 Figure 15. Reverse Bias Safe Operating Area VBE(off) = 1 to 5 V VBE(off) = 0 V BONDING WIRE LIMIT THERMAL LIMIT SECONDARY BREAKDOWN LIMIT 2 20 0.3 3 30 200 1000 10 50 300 1 2 3 5 300 500 700 100 0.03 0.05 MJ16110 II GUARANTEED SAFE OPERATING AREA INFORMATION Figure 16. Switching Safe Operating Area +15 150 Ω 100 µF MTP8P10 MPF930 MPF930 MUR105 MJE210 150 Ω 500 µF VOff 50 Ω +10 MTP12N10 RB1 RB2 1 µF 1 µF 100 Ω MTP8P10 MUR105 MUR1100 T.U.T. MUR870 VCE (650 V MAX) 10 µF 10 mH Note: Test Circuit for Ultra–fast FBSOA Note: RB2 = 0 and VOff = – 5 Volts |
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