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XRP7724 Datasheet(PDF) 8 Page - Exar Corporation |
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XRP7724 Datasheet(HTML) 8 Page - Exar Corporation |
8 / 29 page X XR RP P7 77 72 24 4 Q Qu ua ad d C Ch ha an nn ne ell D Diig giitta all P PW WM M/ /P PF FM M P Prro og grra am mm ma ab blle e P Po ow we err M Ma an na ag ge em me en ntt S Sy ys stte em m © 2012 Exar Corporation 8/29 Rev. 1.0.1 PIN ASSIGNMENT Fig. 4: XRP7724 Pin Assignment PIN DESCRIPTION Name Pin Number Description VCC 41 Input voltage. Place a decoupling capacitor close to the controller IC. This input is used in UVLO fault generation. DVDD 16 1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling capacitor close to the controller IC. VCCD1-2 VCCD3-4 23,34 Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be connected to the LDO5 pin to enable two power rails initially. It is recommended that the other VCCD pin be connected to the output of a 5V switching rail(for improved efficiency or for driving larger external FETs), if available, otherwise this pin may also be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch. AGND 2 Analog ground pin. This is the small signal ground connection. GL_RTN1-4 39,33, 28,22 Ground connection for the low side gate driver. This should be routed as a signal trace with GL. Connect to the source of the low side MOSFET. GL1-GL4 38,32, 27,21 Output pin of the low side gate driver. Connect directly to the gate of an external N- channel MOSFET. GH1-GH4 36,30, 25,19 Output pin of the high side gate driver. Connect directly to the gate of an external N- channel MOSFET. 33 32 31 30 29 28 27 26 24 25 10 1 2 3 4 5 6 7 8 9 LDO3_3 AGND CPLL AVDD VOUT1 VOUT2 VOUT4 GPIO0 GPIO1 GL2 LX2 GH2 BST2 GL_RTN3 GL3 LX3 GH3 BST3 VCCD3-4 VOUT3 Exposed Pad: AGND XRP7724 TQFN 7mm X 7mm 11 SDA 23 GL_RTN2 |
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