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© 2012 Exar Corporation

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Rev. 1.0.1

Name

Pin Number

Description

LX1-LX4

37,31, 26,20

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching

node at the junction between the two external power MOSFETs and the inductor. These

pins are also used to measure voltage drop across bottom MOSFETs in order to provide

output current information to the control engine.

BST1-BST4

35,29, 24,18

High side driver supply pin(s). Connect BST to the external capacitor as shown in the

Typical Application Circuit on page 2. The high side driver is connected between the

BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each

cycle.

GPI0-GPIO1

9,10

These pins can be configured as inputs or outputs to implement custom flags, power

good signals, enable/disable controls and synchronization to an external clock.

PSIO0-PSIO2

13,14,15

Open drain, these pins can be used to control external power MOSFETs to switch loads

on and off, shedding the load for fine grained power management. They can also be

configures as standard logic outputs or inputs just as any of the GPIOs can be

configured, but as open drains require an external pull-up when configured as outputs.

SDA, SCL

11,12

VOUT1-VOUT4

5,6,7,8

Connect to the output of the corresponding power stage. The output is sampled at least

once every switching cycle

LDO5

44

Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of

the IC is in shutdown. This LDO is also used to power the internal Analog Blocks.

LDO3_3

1

Output of the 3.3V standby LDO. This is a micro power LDO that can remain active

while the rest of the IC is in shutdown.

ENABLE

40

If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,

registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be

placed into shutdown.

BFB

42

Input from the 15V output created by the external boost supply. When this pin goes

below a pre-defined threshold, a pulse is created on the low side drive to charge this

output back to the original level. If not used, this pin should be connected to GND.

DGND

17

Digital ground pin. This is the logic ground connection, and should be connected to the

ground plane close to the PAD.

CPLL

3

Connect to a 2.2nF capacitor to GND.

V5EXT

43

External 5V that can be provided. If one of the output channels is configured for 5V,

then this voltage can be fed back to this pin for reduced operating current of the chip

and improved efficiency.

AVDD

4

Output of the internal 1.8V LDO. A decoupling capacitor should be placed between

AVDD and AGND close to the chip.

PAD

45

This is the die attach paddle, which is exposed on the bottom of the part. Connect

externally to the ground plane.

ORDERING INFORMATION

Part Number

Temperature

Range

Marking

Package

Packing

Quantity

Note 1

Address

XRP7724ILB-F

YYWW X

44-pin TQFN

Bulk

Halogen Free

0x28 (7Bit)

XRP7724ILBTR-F

2.5K/Tape & Reel

Halogen Free

XRP7724EVB-DEMO-2P-KIT

Evaluation kit includes XRP7724EVB-DEMO-1 Evaluation Board with Power

“YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable.