REV. 0

AD7677

–6–

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Type

Description

1

AGND

P

Analog Power Ground Pin

2

AVDD

P

Analog Power Pin. Nominally 5 V

3,

NC

No Connect

40–42,

44–48

4

BYTESWAP

DI

Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the

MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is

output on D[7:0].

5OB/

2C

DI

Straight Binary/Binary Two’s Complement. When OB/

2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from

its internal shift register.

6

WARP

DI

Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the

maximum throughput is achievable, and a minimum conversion rate must be applied in order to

guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the

minimum conversion rate.

7

IMPULSE

DI

Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

8

SER/

PAR

DI

Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the

serial interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10

DATA[0:1]

DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/

PAR is HIGH, these outputs

are in high impedance.

11, 12

DATA[2:3] or

DI/O

When SER/

PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data

Output Bus.

DIVSCLK[0:1]

When SER/

PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial

master read after convert mode. These inputs, part of the serial port, are used to slow down if

desired the internal serial clock which clocks the data output. In the other serial modes, these

inputs are not used.

13

DATA[4]

DI/O

When SER/

PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.

or EXT/

INT

When SER/

PAR is HIGH, this input, part of the serial port, is used as a digital select input for

choosing the internal or an external data clock. With EXT/

INT tied LOW, the internal clock

is selected on SCLK output. With EXT/

INT set to a logic HIGH, output data is synchro-

nized to an external clock signal connected to the SCLK input.

14

DATA[5]

DI/O

When SER/

PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC

When SER/

PAR is HIGH, this input, part of the serial port, is used to select the active state

of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

15

DATA[6]

DI/O

When SER/

PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK

When SER/

PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-

nal. It is active in both master and slave mode.

16

DATA[7]

DI/O

When SER/

PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.

or RDC/SDIN

When SER/

PAR is HIGH, this input, part of the serial port, is used as either an external data

input or a read mode selection input depending on the state of EXT/

INT. When EXT/INT is

HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from

two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on

DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/

INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the

data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output

on SDOUT only when the conversion is complete.

17

OGND

P

Input/Output Interface Digital Power Ground

18

OVDD

P

Input/Output Interface Digital Power. Nominally at the same supply than the supply of the

host interface (5 V or 3 V).