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AD7705 Datasheet(PDF) 8 Page - Analog Devices |
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AD7705 Datasheet(HTML) 8 Page - Analog Devices |
8 / 32 page AD7705/AD7706 –8– REV. A Table II. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V Filter First Typical Peak-to-Peak Resolution Bits Notch and O/P –3 dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of Data Rate Frequency 124816 32 64 128 MCLK IN = 2.4576 MHz 50 Hz 13.1 Hz 16 16 16 16 16 16 15 14 60 Hz 15.72 Hz 16 16 16 16 15 14 14 13 250 Hz 65.5 Hz 13 13 13 13 13 13 12 12 500 Hz 131 Hz 10 10 10 10 10 10 10 10 MCLK IN = 1 MHz 20 Hz 5.24 Hz 16 16 16 16 16 16 15 14 25 Hz 6.55 Hz 16 16 16 16 15 14 14 13 100 Hz 26.2 Hz 13 13 13 13 13 13 12 12 200 Hz 52.4 Hz 10 10 10 10 10 10 10 10 OUTPUT NOISE (3 V OPERATION) Table III shows the AD7705/AD7706 output rms noise for the selectable notch and –3 dB frequencies for the part, as selected by FS0 and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a VREF of +1.225 V and a VDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V with the part used in either buffered or unbuffered mode. Table II meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is im- portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of +1.225 V and for either buffered or unbuffered mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Regis- ter set to 0. Table III. Output RMS Noise vs. Gain and Output Update Rate @ 3 V Filter First Typical Output RMS Noise in V Notch and O/P –3 dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of Data Rate Frequency 124816 32 64 128 MCLK IN = 2.4576 MHz 50 Hz 13.1 Hz 3.8 2.4 1.5 1.3 1.1 1.0 0.9 0.9 60 Hz 15.72 Hz 5.1 2.9 1.7 1.5 1.2 1.0 0.9 0.9 250 Hz 65.5 Hz 50 25 14 9.9 5.1 2.6 2.3 2.0 500 Hz 131 Hz 270 135 65 41 22 9.7 5.1 3.3 MCLK IN = 1 MHz 20 Hz 5.24 Hz 3.8 2.4 1.5 1.3 1.1 1.0 0.9 0.9 25 Hz 6.55 Hz 5.1 2.9 1.7 1.5 1.2 1.0 0.9 0.9 100 Hz 26.2 Hz 50 25 14 9.9 5.1 2.6 2.3 2.0 200 Hz 52.4 Hz 270 135 65 41 22 9.7 5.1 3.3 Table IV. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V Filter First Typical Peak-to-Peak Resolution in Bits Notch and O/P –3 dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of Data Rate Frequency 1 2 4 8 16 32 64 128 MCLK IN = 2.4576 MHz 50 Hz 13.1 Hz 16 16 15 15 14 13 13 12 60 Hz 15.72 Hz 16 16 15 14 14 13 13 12 250 Hz 65.5 Hz 13 13 13 13 12 12 11 11 500 Hz 131 Hz 10 10 10 10 10 10 10 10 MCLK IN = 1 MHz 20 Hz 5.24 Hz 16 16 15 15 14 13 13 12 25 Hz 6.55 Hz 16 16 15 14 14 13 13 12 100 Hz 26.2 Hz 13 13 13 13 12 12 11 11 200 Hz 52.4 Hz 10 10 10 10 10 10 10 10 |
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Similar Description - AD7705 |
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