CY7C09089V/99V

CY7C09179V/99V

Document Number: 38-06043 Rev. *G

Page 3 of 28

Functional Description

The CY7C09089V/99V and CY7C09179V/99V are high speed

synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port

static RAMs. Two ports are provided, permitting independent,

simultaneous access for reads and writes to any location in

memory.[4] Registers on control, address, and data lines enable

minimal setup and hold times. In pipelined output mode, data is

registered for decreased cycle time. Clock to data valid

to bypass the pipelined output register to eliminate access

the address is clocked into the device. Pipelined output or

flow-through mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register.

The internal write pulse width is independent of the

LOW-to-HIGH transition of the clock signal. The internal write

pulse is self-timed to enable the shortest possible cycle times.

the internal circuitry to reduce the static power consumption. The

use of multiple Chip Enables enables easier banking of multiple

chips for depth expansion configurations. In the pipelined mode,

the outputs.

Counter enable inputs are provided to stall the operation of the

address input and use the internal address generated by the

internal counter for fast interleaved memory applications. A

port’s burst counter is loaded with the port’s Address Strobe

(ADS). When the port’s Count Enable (CNTEN) is asserted, the

address counter increments on each LOW-to-HIGH transition of

that port’s clock signal. This reads/writes one word from/into

each successive address location until CNTEN is deasserted.

The counter can address the entire memory array and loops

back to the start. Counter Reset (CNTRST) is used to reset the

burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack

(TQFP) packages.

Notes

4. When writing simultaneously to the same location, the final value cannot be guaranteed.

5. See page 9 and page 10 for Load Conditions.